Datasheet STK14CA8C (Infineon) - 5

STK14CA8C
During any STORE operation, regardless of how it is initiated, 3. Read address 0x83E0 Valid READ the STK14CA8C continues to drive the HSB pin LOW, releasing 4. Read address 0x7C1F Valid READ it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for 5. Read address 0x703F Valid READ tLZHSB time after HSB pin returns HIGH. Leave the HSB 6. Read address 0x0C63 Initiate RECALL cycle unconnected if it is not used. Internally, RECALL is a two step procedure. First, the SRAM data
Hardware RECALL (Power-up)
is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again During power-up or after any low power condition ready for read and write operations. The RECALL operation (VCC< VSWITCH), an internal RECALL request is latched. When does not alter the data in the nonvolatile elements. VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
Preventing AutoStore
During this time, HSB is driven low by the HSB driver. The AutoStore function is disabled by initiating an AutoStore
Software STORE
disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate Data is transferred from SRAM to the nonvolatile memory by a the AutoStore disable sequence, the following sequence of CE software address sequence. The STK14CA8C Software STORE or OE controlled read operations must be performed: cycle is initiated by executing sequential CE or OE controlled 1. Read address 0x4E38 Valid READ read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile 2. Read address 0xB1C7 Valid READ data is first performed, followed by a program of the nonvolatile 3. Read address 0x83E0 Valid READ elements. After a STORE cycle is initiated, further input and 4. Read address 0x7C1F Valid READ output are disabled until the cycle is completed. 5. Read address 0x703F Valid READ Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write 6. Read address 0x0B45 AutoStore Disable accesses intervene in the sequence, or the sequence is aborted The AutoStore is reenabled by initiating an AutoStore enable and no STORE or RECALL takes place. sequence. A sequence of read operations is performed in a To initiate the Software STORE cycle, the following read manner similar to the Software RECALL initiation. To initiate the sequence must be performed: AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x0FC0 Initiate STORE cycle 6. Read address 0x0B46 AutoStore Enable The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ If the AutoStore function is disabled or reenabled, a manual sequences. After the sixth address in the sequence is entered, STORE operation (Hardware or Software) must be issued to the STORE cycle commences and the chip is disabled. HSB is save the AutoStore state through subsequent power-down driven LOW. After the t cycles. The part comes from the factory with AutoStore enabled STORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. and 0x00 written in all cells.
Software RECALL Data Protection
Data is transferred from nonvolatile memory to the SRAM by a The STK14CA8C protects data from corruption during low software address sequence. A Software RECALL cycle is voltage conditions by inhibiting all externally initiated STORE initiated with a sequence of read operations in a manner similar and write operations. The low voltage condition is detected when to the Software STORE initiation. To initiate the RECALL cycle, VCC is less than VSWITCH. If the STK14CA8C is in a write mode the following sequence of CE or OE controlled read operations (both CE and WE are LOW) at power-up, after a RECALL or must be performed: STORE, the write is inhibited until the SRAM is enabled after t 1. Read address 0x4E38 Valid READ LZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. 2. Read address 0xB1C7 Valid READ Document Number: 002-23970 Rev. *A Page 5 of 21 Document Outline 1-Mbit (128K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support