Datasheet ISOSD61 (STMicroelectronics) - 8
| Fabricante | STMicroelectronics |
| Descripción | 16-bit isolated Sigma-Delta modulator, single-ended and LVDS interfaces |
| Páginas / Página | 23 / 8 — ISOSD61. Device specifications. Table 9. LVDS transmitter signaling … |
| Formato / tamaño de archivo | PDF / 557 Kb |
| Idioma del documento | Inglés |
ISOSD61. Device specifications. Table 9. LVDS transmitter signaling specifications (ISOSD61L). Parameter. Symbol Min. Typ. Max. Units
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ISOSD61 Device specifications Table 9. LVDS transmitter signaling specifications (ISOSD61L) Parameter Symbol Min. Typ. Max. Units Test Conditions
Output voltage high VOH -0.3 1475 mV RLOAD = 110 Ω +/- 20% Output voltage low VOL 925 mV RLOAD = 110 Ω +/- 20% Output differential voltage |VOD| 240 420 mV RLOAD = 110 Ω +/- 20% Output offset voltage VOS 1125 1200 1275 mV RLOAD = 110 Ω +/- 20% Output current IO 2.2 3.7 mA RLOAD = 110 Ω +/- 20% LVDS load impedance, single ended RL 80 110 140 Ω VCM = 1 V and 1.4 V RL mismatch between both channels ∆RL 10 % RLOAD = 110 Ω +/- 20% MDAT rise time tLH 0.5 5 ns CLOAD = 30 pF RLOAD = 110 Ω +/- 20% MDAT fall time tHL 0.5 5 ns CLOAD = 30pF
Table 10. LVDS receiver signaling specifications Parameter Symbol Min. Typ. Max. Units Conditions
Voltage range VR -0.3 3.6 V RLOAD = 110 Ω +/- 20% Common mode voltage(1) VC 0.05 2.4(2) V RLOAD = 110 Ω +/- 20% Differential input voltage(3) |Vi| 100 mV RLOAD = 110 Ω +/- 20% Differential input hysteresis voltage(4) |VHYS| 25 mV RLOAD = 110 Ω +/- 20% Differential input capacitance Ci 5 pF RLOAD = 110 Ω +/- 20% R Bias resistors(5) PULLUP/ 140 200 260 k Ω PULLDOWN 1. Vc is defined as the voltage that is mid-way between VH and VL. 2. This parameter is guaranteed with Vdd > 4 V. 3. |Vi| defines the minimum differential voltage that is guaranteed to be recognized as a valid input, 1 or 0, by the receiver. 4. |Vhys| defines the minimum voltage separation between the actual |Vi| rising and falling thresholds. 5. A pullup resistor is present between the minus LVDS input and V3.3, and a pulldown resistor is present between plus LVDS input and GND in order to force a ‘0’ value if the LVDS input is floating.
DS13605
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Rev 3 page 8/23
Document Outline Cover image Product status link / summary Features Application Description 1 Device overview 2 Pin description 3 Device specifications 4 Terminology 5 Theory of operation 6 Package description 7 Ordering information Revision history Contents List of tables List of figures
ISOSD61 Device specifications Table 9. LVDS transmitter signaling specifications (ISOSD61L) Parameter Symbol Min. Typ. Max. Units Test Conditions
Output voltage high VOH -0.3 1475 mV RLOAD = 110 Ω +/- 20% Output voltage low VOL 925 mV RLOAD = 110 Ω +/- 20% Output differential voltage |VOD| 240 420 mV RLOAD = 110 Ω +/- 20% Output offset voltage VOS 1125 1200 1275 mV RLOAD = 110 Ω +/- 20% Output current IO 2.2 3.7 mA RLOAD = 110 Ω +/- 20% LVDS load impedance, single ended RL 80 110 140 Ω VCM = 1 V and 1.4 V RL mismatch between both channels ∆RL 10 % RLOAD = 110 Ω +/- 20% MDAT rise time tLH 0.5 5 ns CLOAD = 30 pF RLOAD = 110 Ω +/- 20% MDAT fall time tHL 0.5 5 ns CLOAD = 30pF
Table 10. LVDS receiver signaling specifications Parameter Symbol Min. Typ. Max. Units Conditions
Voltage range VR -0.3 3.6 V RLOAD = 110 Ω +/- 20% Common mode voltage(1) VC 0.05 2.4(2) V RLOAD = 110 Ω +/- 20% Differential input voltage(3) |Vi| 100 mV RLOAD = 110 Ω +/- 20% Differential input hysteresis voltage(4) |VHYS| 25 mV RLOAD = 110 Ω +/- 20% Differential input capacitance Ci 5 pF RLOAD = 110 Ω +/- 20% R Bias resistors(5) PULLUP/ 140 200 260 k Ω PULLDOWN 1. Vc is defined as the voltage that is mid-way between VH and VL. 2. This parameter is guaranteed with Vdd > 4 V. 3. |Vi| defines the minimum differential voltage that is guaranteed to be recognized as a valid input, 1 or 0, by the receiver. 4. |Vhys| defines the minimum voltage separation between the actual |Vi| rising and falling thresholds. 5. A pullup resistor is present between the minus LVDS input and V3.3, and a pulldown resistor is present between plus LVDS input and GND in order to force a ‘0’ value if the LVDS input is floating.
DS13605
-
Rev 3 page 8/23
Document Outline Cover image Product status link / summary Features Application Description 1 Device overview 2 Pin description 3 Device specifications 4 Terminology 5 Theory of operation 6 Package description 7 Ordering information Revision history Contents List of tables List of figures