Datasheet STD30NF06LT4 (STMicroelectronics) - 4

FabricanteSTMicroelectronics
DescripciónN-channel 60 V, 0.022 Ω typ., 35 A STripFET II Power MOSFET in a DPAK package
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Electrical characteristics. STD30NF06LT4. 2 Electrical. characteristics. Table 5. On /off states. Symbol. Parameter. Test conditions

Electrical characteristics STD30NF06LT4 2 Electrical characteristics Table 5 On /off states Symbol Parameter Test conditions

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Electrical characteristics STD30NF06LT4 2 Electrical characteristics
(T = 25 °C unless otherwise specified). C
Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source V breakdown voltage I = 250 μA 60 V (BR)DSS D (V = 0) GS Zero gate voltage V = 60 V 1 μA DS IDSS drain current (V = 0) GS V = 60 V, T =125 °C 10 μA DS C Gate-body leakage I V = ± 20 V ±100 nA GSS GS current (V = 0) DS V Gate threshold voltage V = V , I = 250 μA 1 1.7 2.5 V GS(th) DS GS D V = 10 V, I = 18 A 0.022 0.028 Ω Static drain-source GS D RDS(on) on-resistance V = 5 V, I = 18 A 0.025 0.03 Ω GS D
Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit
C Input capacitance - 1600 pF iss V = 25 V, f = 1 MHz, C Output capacitance DS - 215 pF oss V = 0 GS Reverse transfer C - 60 pF rss capacitance Q Total gate charge - 23 31 nC g V = 48 V, I = 35 A, DD D Q Gate-source charge V = 5 V - 7 nC gs GS (see Figure 14) Q Gate-drain charge - 10 nC gd
Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max Unit
t Turn-on delay time - 30 - ns d(on) V = 30 V, I = 18 A, DD D t Rise time - 105 - ns r R = 4.7 Ω, V = 4.5 V G GS t Turn-off-delay time - 65 - ns d(off) (see Figure 13) t Fall time - 25 - ns f 4/19 DocID026310 Rev 1 Document Outline Figure 1. Internal schematic diagram Table 1. Device summary 1 Electrical ratings Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Avalanche characteristics 2 Electrical characteristics Table 5. On /off states Table 6. Dynamic Table 7. Switching times Table 8. Source drain diode 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance Figure 8. Capacitance variations Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on-resistance vs temperature Figure 11. Normalized V(BR)DSS vs temperature Figure 12. Source-drain diode forward characteristics 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load switching and diode recovery times Figure 16. Unclamped inductive load test circuit Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform 4 Package mechanical data Figure 19. DPAK (TO-252) type A drawing Table 9. DPAK (TO-252) type A mechanical data Figure 20. DPAK (TO-252) type A footprint Figure 21. DPAK (TO-252) type C drawing Table 10. DPAK (TO-252) type C mechanical data Figure 22. DPAK (TO-252) type A footprint 5 Packaging mechanical data Figure 23. Tape for DPAK (TO-252) Figure 24. Reel for DPAK (TO-252) Table 11. DPAK (TO-252) tape and reel mechanical data 6 Revision history Table 12. Document revision history