Datasheet A6275 (Allegro) - 7

Serial-Input Constant-Current Latched LED Driver A6275 with Open LED Detection and Dot Correction TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground) C CLOCK 50% A B SERIAL DATA 50% DATA IN t p SERIAL 50% DATA DATA OUT D E LATCH ENABLE 50% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED t p HIGH = OUTPUT OFF OUT 50% DATA N LOW = OUTPUT ON
A.
Data Active Time Before Clock Pulse Dwg. WP-029-1 (Data Set-Up Time), tsu(D) ...
50 ns B.
Data Active Time After Clock Pulse (Data Hold Time), th(D) ...
20 ns
HIGH = ALL OUTPUTS DISABLED (BLANKED)
C.
Clock Pulse Width, tw(CK) ..
50 ns D.
i T e m t e B n e e w o l C c v i t c A k a o i t n OUTPUT 50% ENABLE and Latch Enable, tsu(L) ...
100 ns
t F pLH
E.
Latch Enable Pulse Width, tw(L) ..
100 ns
t t f r
F.
Output Enable Pulse Width, tw(OE) ...
4.5 s
90% OUT 50% N DATA t pHL 10% NOTE: Timing is representative of a 10 MHz clock. Sig- i n c i f n a g i h y l t p s r e h ee s d a e r a t t a n i b a e l . Dwg. WP-030-1A Max. Clock Transition Time, tr or tf ...
10 s
Serial data present at the input is transferred to the shift g n o l e h t s a H C T A L A N E h s i E L B l e d a c i l p p A . h g i h t s n o i h w e e r register on the logic 0-to-logic 1 transition of the CLOCK input the latches are bypassed (LATCH ENABLE tied high) will pulse. On succeeding CLOCK pulses, the registers shift data in- e r e r i u q h t a h t t e P T U O L B A N E T U p n i E u e b t h u d h g i g n i r e s r a i l formation towards the SERIAL DATA OUTPUT. The serial data data entry. must appear at the input prior to the rising edge of the CLOCK When the OUTPUT ENABLE input is high, the output sink input waveform. v i r d e a s r r a s i d e b e l ( d F O ) F n i e h T . o f a m r n o i t s e r o t d i n th a l e t h c e s Information present at any register is transferred to the is not affected by the OUTPUT ENABLE input. With the OUT- respective latch when the LATCH ENABLE is high (serial-to- PUT ENABLE input low, the outputs are con trolled by the state p l a r a e l n o c l . ) n o i s r e v e h c t a l e h T c s o o t e u n i t n c c a t p e e n w a d a t a s t f o r i e h e r p s e t c e v i t a l c e h s. Allegro MicroSystems, Inc. 6 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com