Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 7

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ADSP-BF512 /BF514 /BF516 /BF518
Examples of DMA types supported by the DMA controller minute, hour, or day clock ticks, interrupt on programmable include: stopwatch countdown, or interrupt at a programmed alarm • A single, linear buffer that stops upon completion time. • A circular, auto-refreshing buffer that interrupts on each The 32.768 kHz input clock frequency is divided down to a 1 Hz full or fractionally full buffer signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a • 1-D or 2-D DMA using a linked list of descriptors 24-hour counter, and an 32,768-day counter. • 2-D DMA using an array o f descriptors, specifying only the When enabled, the alarm function generates an interrupt when base DMA address within a common page the output of the timer matches the programmed value in the In addition to the dedicated peripheral DMA channels, there are alarm control register. There are two alarms: The first alarm is two memory DMA channels that transfer data between the vari- for a time of day. The second alarm is for a day and time of ous memories of the processor system. This enables transfers of that day. blocks of data between any of the memories—including external The stopwatch function counts down from a programmed SDRAM, ROM, SRAM, and flash memory—with minimal value, with one-second resolution. When the stopwatch is processor intervention. Memory DMA transfers can be con- enabled and the counter underflows, an interrupt is generated. trolled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. Like the other peripherals, the RTC can wake up the processor from sleep mode upon generation of any RTC wakeup event. The processors also have an external DMA controller capability Additionally, an RTC wakeup event can wake up the processor via dual external DMA request signals when used in conjunc- from deep sleep mode or cause a transition from the hibernate tion with the external bus interface unit (EBIU). This state. functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communica- Connect RTC signals RTXI and RTXO with external compo- tions peripherals. It allows control of the number of data nents as shown in Figure 4. transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow mem-
RTXI RTXO
ory DMA to have an increased priority on the external bus
R1
relative to the core.
PROCESSOR PERIPHERALS X1
The ADSP-BF51x processors contain a rich set of peripherals
C1 C2
connected to the core via several high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see Figure 2). The processors contain ded- icated network communication modules and high speed serial
SUGGESTED COMPONENTS:
and parallel ports, an interrupt controller for flexible manage-
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
ment of interrupts from the on-chip peripherals or external
C1 = 22 pF
sources, and power management control functions to tailor the
C2 = 22 pF
performance and power characteristics of the processor and sys-
R1 = 10 M
:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
tem to many application scenarios.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
All of the peripherals, except for the general-purpose I/O, rotary counter, TWI, three-phase PWM, real-time clock, and timers, Figure 4. External Components for RTC are supported by a flexible DMA structure. There are also sepa- rate memory DMA channels dedicated to data transfers
Watchdog Timer
between the processor's various memory spaces, including The ADSP-BF51x processors include a 32-bit timer that can be external SDRAM and asynchronous memory. Multiple on-chip used to implement a software watchdog function. A software buses provide enough bandwidth to keep the processor core watchdog can improve system availability by forcing the proces- running along with activity on all of the on-chip and external sor to a known state through generation of a hardware reset, peripherals. nonmaskable interrupt (NMI), or general-purpose interrupt, if
Real-Time Clock
the timer expires before being reset by software. The program- mer initializes the count value of the timer, enables the The real-time clock (RTC) provides a robust set of digital watch appropriate interrupt, then enables the timer. Thereafter, the features, including current time, stopwatch, and alarm. The software must reload the counter before it counts to zero from RTC is clocked by a 32.768 kHz crystal external to the proces- the programmed value. This protects the system from remain- sors. The RTC peripheral has a dedicated power supply so that it ing in an unknown state where software, which would normally can remain powered up and clocked even when the rest of the reset the timer, has stopped running due to an external noise processor is in a low power state. The RTC provides several pro- condition or software error. grammable interrupt options, including interrupt per second, Rev. E | Page 7 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide