Datasheet ADSP-BF512, BF514, BF516, BF518 (Analog Devices) - 3

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ADSP-BF512 /BF514 /BF516 /BF518 GENERAL DESCRIPTION
The ADSP-BF512/ADSP-BF514/ADSP-BF516/ADSP-BF518
PORTABLE LOW POWER ARCHITECTURE
processors are members of the Blackfin® family of products, Blackfin processors provide world-class power management incorporating the Analog Devices/Intel Micro Signal Architec- and performance. They are produced with a low power and low ture (MSA). Blackfin processors combine a dual-MAC state-of- voltage design methodology and feature on-chip dynamic the-art signal processing engine, the advantages of a clean, power management, which is the ability to vary both the voltage orthogonal RISC-like microprocessor instruction set, and sin- and frequency of operation to significantly lower overall power gle-instruction, multiple-data (SIMD) multimedia capabilities consumption. This capability can result in a substantial reduc- into a single instruction-set architecture. tion in power consumption, compared with just varying the The processors are completely code compatible with other frequency of operation. This allows longer battery life for Blackfin processors. portable appliances.
Table 1. Processor Comparison SYSTEM INTEGRATION
The ADSP-BF51x processors are highly integrated system-on-a- chip solutions for the next generation of embedded network
-BF512 -BF514 -BF516 -BF518
connected applications. By combining industry-standard inter- faces with a high performance signal processing core, cost-
Feature ADSP ADSP ADSP ADSP
effective applications can be developed quickly, without the IEEE-1588 – – – 1 need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC with Ethernet MAC – – 1 1 IEEE-1588 support (ADSP-BF518 only), an RSI controller, a RSI – 1 1 1 TWI controller, two UART ports, two SPI ports, two serial ports TWI 1 1 1 1 (SPORTs), nine general-purpose 32-bit timers (eight with PWM SPORTs 2 2 2 2 capability), 3-phase PWM for motor control, a real-time clock, a UARTs 2 2 2 2 watchdog timer, and a parallel peripheral interface (PPI). SPIs 2 2 2 2
BLACKFIN PROCESSOR CORE
GP Timers 8 8 8 8 As shown in Figure 2, the Blackfin processor core contains two Watch dog Timers 1 1 1 1 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, RTC 1 1 1 1 four video ALUs, and a 40-bit shifter. The computation units PPI 1 1 1 1 process 8-, 16-, or 32-bit data from the register file. Ro tary Counter 1 1 1 1 The compute register file contains eight 32-bit registers. When 3-Ph ase P WM Pairs 3 3 3 3 performing compute operations on 16-bit operand data, the GPIOs 40 40 40 40 register file operates as 16 independent 16-bit registers. All L1 Instruction SRAM 32K operands for compute operations come from the multiported register file and instruction constant fields. L1 Instruction SRAM/Cache 16K L1 Data SRAM 32K Each MAC can perform a 16-bit by 16-bit multiply in each (bytes) y cycle, accumulating the results into the 40-bit accumulators. L1 Data SRAM/Cache 32K mor Signed and unsigned formats, rounding, and saturation e L1 Scratchpad 4K M are supported. L3 Boot ROM 32K The ALUs perform a traditional set of arithmetic and logical Maximum Speed Grade 400 MHz operations on 16-bit or 32-bit data. In addition, many special Package Options 176-Lead LQFP_EP (with instructions are included to accelerate various signal processing Exposed Pad) tasks. These include bit operations such as field extract and pop- 168-Ball CSP_BGA ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video By integrating a rich set of industry-leading system peripherals instructions include byte alignment and packing operations, and memory, Blackfin processors are the platform of choice for 16-bit and 8-bit adds with clipping, 8-bit average operations, next-generation applications that require RISC-like program- and 8-bit subtract/absolute value/accumulate (SAA) operations. mability, multimedia support, and leading-edge signal The compare/select and vector search instructions are also processing in one integrated package. provided. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible. Rev. E | Page 3 of 63 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time Programmable Memory I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Real-Time Clock Watchdog Timer Timers 3-Phase PWM General-Purpose (GP) Counter Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports 2-Wire Interface (TWI) Removable Storage Interface (RSI) 10/100 Ethernet MAC IEEE 1588 Support Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) Code Security with Lockbox Secure Technology Lockbox Secure Technology Disclaimer Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Interface Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 176-Lead LQFP_EP Lead Assignment 168-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide