Datasheet ADSP-BF504 (Analog Devices)

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Blackfin Embedded Processor ADSP-BF504 FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Two 32-bit up/down counters with rotary support Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, Eight 32-bit timers/counters with PWM support 40-bit shifter Two 3-phase 16-bit center-based PWM units RISC-like register and instruction model for ease of 2 dual-channel, full-duplex synchronous serial ports programming and compiler-friendly support (SPORTs), supporting eight stereo I2S channels Advanced debug, trace, and performance monitoring 2 serial peripheral interface (SPI) compatible ports Accepts a range of supply voltages for internal and I/O opera- 2 UARTs with IrDA support tions. See Operating Conditions Parallel peripheral interface (PPI), supporting ITU-R 656 Off-chip voltage regulator interface video data formats 88-lead (12 mm
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12 mm) LFCSP package Removable storage interface (RSI) controller for MMC, SD, MEMORY SDIO, and CE-ATA ADC controller module (ACM), providing a glueless interface 68K bytes of L1 SRAM (processor core-accessible) memory between Blackfin processor and external ADC (See Table 1 for L1 and L3 memory size details) Controller Area Network (CAN) controller External (interface-accessible) memory controller with glue- 2-wire interface (TWI) controller less support for boot ROM 12 peripheral DMAs Flexible booting options from SPI memory or from host 2 memory-to-memory DMA channels devices including SPI, PPI, and UART Event handler with 52 interrupt inputs Memory management unit providing memory protection 35 general-purpose I/Os (GPIOs), with programmable hysteresis Debug/JTAG interface On-chip PLL capable of frequency multiplication WATCHDOG TIMER COUNTER1–0 GPIO TIMER7–0 VOLTAGE REGULATOR INTERFACE JTAG TEST AND EMULATION PERIPHERAL PWM 1–0 PORT F ACCESS BUS SPORT1–0 PORT G INTERRUPT SPI1–0 CONTROLLER
B
UART1–0 PORT H L1 INSTRUCTION L1 DATA PPI DMA MEMORY MEMORY CONTROLLER DMA RSI EAB 16 ACCESS BUS DCB ACM DEB CAN BOOT MEMORY PORT CONTROL TWI ROM
Figure 1. Processor Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide