Datasheet ADP5054 (Analog Devices) - 8

FabricanteAnalog Devices
DescripciónQuad Buck Regulator Integrated Power Solution
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ADP5054. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 4. Parameter1 Rating. THERMAL RESISTANCE. Table 5. Thermal Resistance

ADP5054 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4 Parameter1 Rating THERMAL RESISTANCE Table 5 Thermal Resistance

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ADP5054 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a
Parameter1 Rating
stress rating only; functional operation of the product at these PVIN1 to PGND −0.3 V to +18 V or any other conditions above those indicated in the operational PVIN2 to PGND −0.3 V to +18 V section of this specification is not implied. Operation beyond PVIN3 to PGND3 −0.3 V to +18 V the maximum operating conditions for extended periods may PVIN4 to PGND4 −0.3 V to +18 V affect product reliability. SW1 to PGND −0.3 V to +18 V SW2 to PGND −0.3 V to +18 V
THERMAL RESISTANCE
SW3 to PGND3 −0.3 V to +18 V θJA is specified for the worst-case conditions, that is, a device SW4 to PGND4 −0.3 V to +18 V soldered in a circuit board for surface-mount packages. PGND to Ground −0.3 V to +0.3 V PGND3 to Ground −0.3 V to +0.3 V
Table 5. Thermal Resistance
PGND4 to Ground −0.3 V to +0.3 V
Package Type θJA θJC Unit
BST1 to SW1 −0.3 V to +6.5 V 48-Lead LFCSP 28.4 10.1 °C/W BST2 to SW2 −0.3 V to +6.5 V BST3 to SW3 −0.3 V to +6.5 V
ESD CAUTION
BST4 to SW4 −0.3 V to +6.5 V DL1 to PGND −0.3 V to +6.5 V DL2 to PGND −0.3 V to +6.5 V CFG12, CFG34 to Ground −0.3 V to +6.5 V EN1, EN2, EN3, EN4 to Ground −0.3 V to +6.5 V VREG to Ground −0.3 V to +6.5 V SYNC/MODE to Ground −0.3 V to +6.5 V RT to Ground −0.3 V to +3.6 V PWRGD to Ground −0.3 V to +6.5 V FB1, FB2, FB3, FB4 to Ground 2 −0.3 V to +3.6 V COMP1, COMP2, COMP3, COMP4 to Ground −0.3 V to +3.6 V Storage Temperate Range −65°C to +150°C Operational Junction Temperature Range −40°C to +125°C 1 The exposed pad is the analog ground for the ADP5054. See Table 6. 2 The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable output voltage models of the ADP5054. Rev. G | Page 8 of 31 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGE INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK PULSE SKIP IN MAXIMUM DUTY SHORT-CIRCUIT PROTECTION (SCP) LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUIT FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE