Datasheet AD5560 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs |
| Páginas / Página | 66 / 8 — AD5560. Data Sheet. Parameter. Min. Typ. Max. Unit. Test … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 2.1 Mb |
| Idioma del documento | Inglés |
AD5560. Data Sheet. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
SYS_FORCE Voltage Range AVSS AVDD V Current Carrying Capability1 −25 +25 mA Leakage Current −2.5 +2.5 nA SYS_FORCE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 35 Ω AVDD = 16.5 V, AVSS = −16.5 V Pin Capacitance1 5 pF SYS_DUTGND Voltage Range AVSS AVDD V Path On Resistance 300 400 Ω AVDD = 16.5 V, AVSS = −16.5 V CURRENT CLAMP Clamp Accuracy Programmed Programmed % of FS MI gain = 20, with clamp separation of 2 V, and clamp value clamp value + 10 1 V separation from AGND/0 A Programmed Programmed % of FS MI gain = 10, with clamp separation of 2 V, and clamp value clamp value + 20 1 V separation from AGND/0 A VCLL to VCLH1 2 V 10% of FSCR (MI gain = 20), 20% of FSCR (MI gain = 10), restriction to prevent both clamps activating together VCLL to 0 A1 1 V 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level VCLH to 0 A1 1 V 5% of FSCR (MI gain 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level Clamp Activation Response Time1 20 100 μs Measured from BUSY going low to visible clamping Clamp Recovery1 2 5 μs Measured from BUSY going low to visible recovery Alarm Delay 1 50 μs Time for CLALM to flag FORCE AMPLIFER Slew Rate1 1 V/µs Fastest slew rate, controlled via serial interface 0.312 V/µs Slowest slew rate, controlled via serial interface Maximum Stable Load Capacitance1 160 µF Voltage Overshoot/Undershoot1 5 % Of programmed value (≥1 V) SETTLING TIME (FORCE AMPLIFER) Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value 380 nF, ESR 74 to 140 mΩ) FV (1200 mA EXTFORCE1 Range)1 16 25 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load FV (900 mA EXTFORCE1 Range)1 18 30 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load FV (500 mA EXTFORCE2 Range)1 34 53 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load FV (300 mA EXTFORCE2 Range)1 25 50 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load FV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load FV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load FV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load FV (25 µA Range)1, 3 400 600 µs 10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load FV (5 µA Range)1, 3 20 40 µs 1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load Compensation Register 1 = 0x8880 (1.7 μF to 2.9 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 16 25 µs 3 V step, CDUT = 2.2 µF, full dc load FV (100 mA EXTFORCE2 Range)1 60 80 µs 8 V step, CDUT = 2.2 µF, full dc load Compensation Register 1 = 0xB880 (7.9μF to 13 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 55 70 µs 3 V step, CDUT = 10 µF, full dc load FV (100 mA EXTFORCE2 Range)1 210 260 µs 8 V step, CDUT = 10 µF, full dc load Compensation Register 1 = 0xC880 (13 μF to 22 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 65 80 µs 3 V step, CDUT = 20 µF, full dc load FV (100 mA EXTFORCE2 Range)1 310 370 µs 8 V step, CDUT = 20 µF, full dc load Rev. E | Page 8 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE
AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
SYS_FORCE Voltage Range AVSS AVDD V Current Carrying Capability1 −25 +25 mA Leakage Current −2.5 +2.5 nA SYS_FORCE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 35 Ω AVDD = 16.5 V, AVSS = −16.5 V Pin Capacitance1 5 pF SYS_DUTGND Voltage Range AVSS AVDD V Path On Resistance 300 400 Ω AVDD = 16.5 V, AVSS = −16.5 V CURRENT CLAMP Clamp Accuracy Programmed Programmed % of FS MI gain = 20, with clamp separation of 2 V, and clamp value clamp value + 10 1 V separation from AGND/0 A Programmed Programmed % of FS MI gain = 10, with clamp separation of 2 V, and clamp value clamp value + 20 1 V separation from AGND/0 A VCLL to VCLH1 2 V 10% of FSCR (MI gain = 20), 20% of FSCR (MI gain = 10), restriction to prevent both clamps activating together VCLL to 0 A1 1 V 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level VCLH to 0 A1 1 V 5% of FSCR (MI gain 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level Clamp Activation Response Time1 20 100 μs Measured from BUSY going low to visible clamping Clamp Recovery1 2 5 μs Measured from BUSY going low to visible recovery Alarm Delay 1 50 μs Time for CLALM to flag FORCE AMPLIFER Slew Rate1 1 V/µs Fastest slew rate, controlled via serial interface 0.312 V/µs Slowest slew rate, controlled via serial interface Maximum Stable Load Capacitance1 160 µF Voltage Overshoot/Undershoot1 5 % Of programmed value (≥1 V) SETTLING TIME (FORCE AMPLIFER) Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value 380 nF, ESR 74 to 140 mΩ) FV (1200 mA EXTFORCE1 Range)1 16 25 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load FV (900 mA EXTFORCE1 Range)1 18 30 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load FV (500 mA EXTFORCE2 Range)1 34 53 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load FV (300 mA EXTFORCE2 Range)1 25 50 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load FV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load FV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load FV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load FV (25 µA Range)1, 3 400 600 µs 10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load FV (5 µA Range)1, 3 20 40 µs 1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load Compensation Register 1 = 0x8880 (1.7 μF to 2.9 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 16 25 µs 3 V step, CDUT = 2.2 µF, full dc load FV (100 mA EXTFORCE2 Range)1 60 80 µs 8 V step, CDUT = 2.2 µF, full dc load Compensation Register 1 = 0xB880 (7.9μF to 13 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 55 70 µs 3 V step, CDUT = 10 µF, full dc load FV (100 mA EXTFORCE2 Range)1 210 260 µs 8 V step, CDUT = 10 µF, full dc load Compensation Register 1 = 0xC880 (13 μF to 22 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 65 80 µs 3 V step, CDUT = 20 µF, full dc load FV (100 mA EXTFORCE2 Range)1 310 370 µs 8 V step, CDUT = 20 µF, full dc load Rev. E | Page 8 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE