Data SheetAD5522AGNDAVSSAVDDDVCCDGNDCCOMP0ENVREF16-BIT1616CH0EXTFOH0X1 REGCLH DACCLHCFF0X2 REGSW316M REGREFGND×216C REG×2OFFSET DACINTERNAL RANGE16–FINSELECT16×6SW1(±5µA, ±20µA, ±200µA, ±2mA)1616-BITX1 REG+16 FIN DAC+M REGAGNDFOH0X2 REGFORCEC REGMEASVHAMPLIFIERSW5×6(Hi-Z)–RSENSESW2SW4SW64kΩ161616-BITX1 REGCLL DACCLLEXTMEASIH016X2 REGVMID TOM REG×2+16CENTEREXTERNALC REGSW8SW10–×2I RANGERSENSE2kΩ SW7(CURRENTS+×5 OR ×10EXTMEASIL0UP TO ±80mA)MEASOUT–+MEASOUT0MUX AND GAIN–SW9×1/×0.2SW12TEMP4kΩSENSORMEASUREAGND16CURRENTSW11MEASVH0×6IN-AMP16×6+16X1 REGSW161616-BIT–M REGCPH DACX2 REGAGNDSW13DUTC REG+GUARD0×1GUARD AMPDUTGND16CPHDUTGND16×6–+SW14×6GUARDIN0/CPL16-BIT–16X1 REG16DUTGND0CPL DACM REGX2 REG––++MEASUREC REGVOLTAGESW15COMPARATORIN-AMPCPOL0/SCLK10kΩAGNDCPOH0/SDIEXTFOH1CFF1CCOMP1FOH1MEASOUT1CH1EXTMEASIH1CPOL1/SYNCEXTMEASIL1CPOH1/SDOMEASVH1AGNDGUARD1GUARDIN1/DUTGND1MUXSYS_SENSEMUXSYS_FORCEEXTFOH2CFF2CCOMP2FOH2MEASOUT2CPOL2/CPO0EXTMEASIH2CPOH2/CPO1CH2EXTMEASIL2AGNDMEASVH2GUARD2GUARDIN2/DUTGND2ENCCOMP3EXTFOH316-BIT1616X1 REGCLH DACCLHX2 REGSW3CFF316M REG×216C REG×2OFFSET DACCH3INTERNAL RANGE16SELECT–FIN16×6SW1(±5µA, ±20µA, ±200µA, ±2mA)1616-BIT+X1 REG16 FIN DAC+M REGX2 REGAGNDFORCEFOH3C REGAMPLIFIERMEASVHSW5×6(Hi-Z)–RSENSESW2SW64kΩ161616-BITSW4X1 REGCLL DACCLLEXTMEASIH316X2 REGVMID TOM REG×2+16CENTEREXTERNALC REGSW10–SW8×2I RANGERSENSE2kΩ SW7(CURRENTS+x5 or x10EXTMEASIL3UP TO ±80mA)MEASOUT–+MEASOUT3MUX AND GAIN–SW9x1/x0.2SW12TEMP4kΩSENSORMEASURE16AGNDCURRENTSW11MEASVH3×6IN-AMP16×6+16X1 REG1616-BIT–M REGCPH DACX2 REGAGNDSW13C REG+GUARD3DUTSW16x1GUARD AMPDUTGND16CPH16×6–+×6SW14CPLGUARDIN3/16-BIT–16X1 REG16 CPL DACDUTGND3M REGX2 REG––++MEASUREC REGVOLTAGESW15IN-AMPCOMPARATOR10kΩAGNDDUTGND16-BITTO ALL DACTO16OUTPUTTEMPOFFSETMEASOUTSW15aTMPALMAMPLIFIERSSENSORDACMUX16SERIAL10kΩCLAMP AND 002 CGALMPOWER-ONINTERFACEGUARDAGNDALARMRESET 06197- RESET SDO SCLK SDI SYNC BUSY LOADSPI/CPOL3/CPOH3/LVDSCPO2CPO3 Figure 2. Detailed Block Diagram Rev. F | Page 5 of 64 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide