AD6295V/DIV5V/DIV+10V0VVOUTVOUT0V–10VOUTPUTOUTPUT1mV = 0.01%1mV = 0.01%ERRORERROR 4 7 02 1mV/DIV10µs/DIV 02 1mV/DIV10µs/DIV 3- 3- 78 78 00 00 Figure 25. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ Figure 28. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ 350300N = 2180N = 2180300n ≈ 200 PCS. FROM250n ≈ 200 PCS. FROM10 ASSEMBLY LOTS10 ASSEMBLY LOTS250SSTT200UNI200UNIFFOO150RRBE150BENUMNUM1001005050 25 28 0 0 3- 3- 78 78 0 00 0 00 –150–100–50050100150–900–600–3000300600900COMMON-MODE REJECTION RATIO (ppm)OFFSET VOLTAGE (µV) Figure 26. Typical Distribution of Common-Mode Rejection; Package Option N-8 Figure 29. Typical Distribution of Offset Voltage; Package Option N-8 400400N = 2180N = 2180350350n ≈ 200 PCS. FROMn ≈ 200 PCS. FROM10 ASSEMBLY LOTS10 ASSEMBLY LOTS300300SSTT250250UNIUNIFFO200O200RRBEBE150150NUMNUM1001005050 26 29 0 0 3- 3- 78 78 0 00 0 00 –600–400–2000200400600–600–400–2000200400600–1 GAIN ERROR (ppm)+1 GAIN ERROR (ppm) Figure 27. Typical Distribution of −1 Gain Error; Package Option N-8 Figure 30. Typical Distribution of +1 Gain Error; Package Option N-8 Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS BASIC CONNECTIONS SINGLE-SUPPLY OPERATION SYSTEM-LEVEL DECOUPLING AND GROUNDING USING A LARGE SENSE RESISTOR OUTPUT FILTERING OUTPUT CURRENT AND BUFFERING A GAIN OF 19 DIFFERENTIAL AMPLIFIER ERROR BUDGET ANALYSIS EXAMPLE 1 ERROR BUDGET ANALYSIS EXAMPLE 2 OUTLINE DIMENSIONS ORDERING GUIDE