Datasheet ADA4830-1, ADA4830-2 (Analog Devices) - 8

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ADA4830-1/ADA4830-2 Data Sheet 1 EF ND1 VS1 NA1 VR G + E 16 15 14 13 INP1 1 12 VOUT1 INN1 2 ADA4830-2 11 STB1 INN2 3 TOP 10 STB2 VIEW INP2 4 9 VOUT2 5 6 7 8 2 EF ND2 VS2 NA2 G + E VR NOTES 1. EXPOSED PAD ON BOTTOM SIDE OF PACKAGE. NOT CONNECTED ELECTRICALLY, BUT SHOULD BE SOLDERED TO A METALIZED AREA
004
ON THE PCB TO MINIMIZE THERMAL RESISTANCE.
10020- Figure 5. ADA4830-2 Pin Configuration
Table 6. ADA4830-2 P in Function Descriptions Pin No. Mnemonic Description
1, 4 INP1, INP2 Positive Inputs. 2, 3 INN1, INN2 Negative Inputs. 5, 16 VREF2, VREF1 Voltage Reference Inputs. Sets the output dc bias voltage. Internally biased to +VS/2 when left floating. See the Applications Information section. 6, 15 GND2, GND1 Power Supply Ground Pins. 7, 14 +VS2, +VS1 Positive Power Supply Pins. These pins must be connected together, to the same voltage. Bypass these pins with a 0.1 µF capacitor to ground. 8, 13 ENA2, ENA1 Enable Pins. Connect to +VS or float for normal operation and to ground for device disable. 9, 12 VOUT2, VOUT1 Amplifier Outputs. 10, 11 STB2, STB1 Short-to-Battery Indicator Output Pins. A logic low indicates an overvoltage condition (short-to-battery), whereas a logic high indicates normal operation. An open-drain configuration requires an external pull-up resistor. EPAD Exposed Pad. The exposed pad is located on the bottom side of the package. The pad is not connected electrically, but should be soldered to a metalized area on the PCB to minimize thermal resistance. Rev. C | Page 8 of 22 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications 5 V Operation 3.3 V Operation Absolute Maximum Ratings Thermal Resistance Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Core Amplifier Overvoltage (Short-to-Battery) Protection Short-to-Battery Output Flag ESD Protection Power Supply Pins (ADA4830-2) Applications Information Methods of Transmission Pseudo Differential Mode (Unbalanced Source Termination) Pseudo Differential Mode (Balanced Source Impedance) Fully Differential Mode Voltage Reference (VREF Pin) Input Common-Mode Range Short-to-Battery Output Flag Pin Enable/Disable Modes (ENA Pin) PCB Layout Exposed Paddle (EPAD) Connection Using the ADA4830-2 as a Low Cost Video Switch Driving Capacitive Loads Typical Applications Circuits Fully DC-Coupled Transmission Line Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products