Datasheet AD626 (Analog Devices) - 10

AD626
necessary to min i mize gain error. Also, any mis match be tween the
+INPUT
total source re sis tance at each input will af fect gain ac cu ra cy and common -mode rejection (CMR). For ex am ple: when operating at
–IN 200k
⍀
200k
⍀
+IN
a gain of 10, an 80 ⍀ mismatch in the source re sis tance between
–INPUT 1 8
the inputs will degrade CMR to 68 dB.
1/6 ANALOG
The output buffer, A2, operates at a gain of 2 or 20, thus setting
2 G = 100 7 GND G = 30
the overall, precalibrated gain of the AD626 (with no ex ter nal com po nents) at 10 or 100. The gain is set by the feedback net work
–VS 3 –V +V 6 S S +VS
around amplifi er A2.
0.1
␮
F 100k
⍀
0.1
␮
F
The output of amplifi er A2 relies on a 10 k⍀ resistor to –V
FILTER OUT
S for
4 G = 2 5 OUTPUT
“pull-down.” For single-supply operation, (–VS = “GND”), A2
AD626
can drive a 10 k⍀ ground ref er enced load to at least +4.7 V. The min i mum, nominally “zero,” output voltage will be 30 mV. For dual-supply op er a tion (±5 V), the positive output voltage swing Figure 6. AD626 Confi gured for a Gain of 100 will be the same as for a single supply. The negative swing will be
+INPUT
to –2.5 V, at G = 100, limited by the ratio: R15 R14
200k
⍀
200k
⍀ –V
–IN +IN
S × +
–INPUT
R
1 8
13 + R14 + R15
1/6
The negative range can be extended to –3.3 V (G = 100) and –4 V
RH ANALOG 2 G = 100 7 GND
(G = 10) by add ing an external 10 k⍀ pull-down from the out put
RG G = 30
to –VS. This will add 0.5 mA to the AD626’s qui es cent cur rent, bringing the total to 2 mA.
–V 3 –V +V S 6 +V S S S 0.1
␮
F 100k
⍀
0.1
␮
F
The AD626’s 100 kHz bandwidth at G = 10 and 100 (a 10 MHz
FILTER OUT
gain bandwidth) is much higher than can be obtained with low
CF 4 G = 2 5 OUTPUT FILTER
power op amps in discrete dif fer en tial amplifi er circuits. Fur ther -
AD626 (OPTIONAL)
more, the AD626 is stable driving capacitive loads up to 50 pF
1
(G10) or 200 pF (G100). Capacitive load drive can be increased
CORNER FREQUENCY OF FILTER = 2
␲
CF (100k
⍀
)
to 200 pF (G10) by connecting a 100 ⍀ resistor in series with the
RESISTOR VALUES FOR GAIN ADJUSTMENT
AD626’s output and the load.
GAIN RANGE RG(
⍀
) RH(
⍀
) ADJUSTING THE GAIN OF THE AD626 11 – 20 100k 4.99k
The AD626 is easily confi gured for gains of 10 or 100. Figure 5
20 – 40 10k 802 40 – 80 1k 80
shows that for a gain of 10, Pin 7 is simply left un con nect ed; simi-
80 – 100 100 2
larly, for a gain of 100, Pin 7 is grounded, as shown in Fig ure 6. Gains between 10 and 100 are easily set by connecting a vari able Figure 7. Recommended Circuit for Gain Adjustment resistance between Pin 7 and Analog GND, as shown in Fig ure 7. Because the on-chip resistors have an absolute tol er ance of ±20%
SINGLE-POLE LOW-PASS FILTERING
(although they are ratio matched to within 0.1%), at least a 20% A low-pass fi lter can be easily implemented by using the fea tures adjustment range must be provided. The values shown in the provided by the AD626. table in Figure 7 provide a good trade-off be tween gain set range and resolution, for gains from 11 to 90. By simply connecting a capacitor between Pin 4 and ground, a single-pole low-pass fi lter is created, as shown in Figure 8.
+INPUT +INPUT –IN 200k
⍀
200k
⍀
+IN –INPUT 1 8 –IN 200k
⍀
200k
⍀
+IN –INPUT 1 8 1/6 NOT 2 ANALOG G = 10 7 1/6 CONNECTED GND ANALOG G = 30 2 G = 100 7 GND G = 30 –VS 3 –VS +VS 6 +VS 3 –V +V 6 +10V S S 0.1
␮
F 100k
⍀
0.1
␮
F FILTER OUT 100k
⍀
0.1
␮
F 4 G = 2 5 OUTPUT FILTER OUT 4 G = 2 5 OUTPUT AD626 CF AD626
Figure 5. AD626 Confi gured for a Gain of 10
1 CORNER FREQUENCY OF FILTER = 2
␲
CF (100k
⍀
)
Figure 8. A One-Pole Low-Pass Filter Circuit Which Operates from a Single +10 V Supply –10– REV. D Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION CONECTION DIAGRAM SPECIFICATIONS SINGLE SUPPLY DUAL SUPPLY ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Typical Performance Characteristics THEORY OF OPERATION ADJUSTING THE GAIN OF THE AD626 SINGLE-POLE LOW-PASS FILTERING CURRENT SENSOR INTERFACE BRIDGE APPLICATION OUTLINE DIMENSIONS Revision History