Datasheet AD8324 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 3.3 V DOCSIS 2.0 Upstream Cable Line Driver |
| Páginas / Página | 16 / 8 — AD8324. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. –40. VOUT = … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 427 Kb |
| Idioma del documento | Inglés |
AD8324. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. –40. VOUT = 62dBmV @ DEC 60. VOUT = 61dBmV @ DEC 60. –50. –60
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AD8324 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –40 –40 VOUT = 62dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 –50 –50 VOUT = 62dBmV @ DEC 60 V –60 OUT = 61dBmV @ DEC 60 –60 VOUT = 60dBmV @ DEC 60 DISTORTION (dBc) DISTORTION (dBc) –70 –70 VOUT = 60dBmV @ DEC 60 –80
04339-0-007
–80
04339-0-010
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 7. Second-Order Harmonic Distortion vs. Frequency Figure 10. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers for Various Output Powers
–40 –40 V V OUT = 61dBmV @ DEC 60 OUT = 61dBmV @ DEC 60 TA = +25°C T –50 A = +85°C –50 TA = –40°C –60 T T –60 A = –40°C A = +25°C DISTORTION (dBc) DISTORTION (dBc) –70 –70 TA = +85°C –80
04339-0-008
–80
04339-0-011
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 8. LFCSP Second-Order Harmonic Distortion Figure 11. LFCSP Third-Order Harmonic Distortion vs. Frequency for Various Temperatures vs. Frequency for Various Temperatures
–40 –40 V V OUT = 61dBmV @ DEC 60 OUT = 61dBmV @ DEC 60 TA = +25°C TA = +70°C –50 –50 TA = +25°C TA = –25°C –60 –60 TA = –25°C DISTORTION (dBc) DISTORTION (dBc) –70 –70 TA = +70°C –80
04339-0-009
–80
04339-0-012
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 9. QSOP Second-Order Harmonic Distortion Figure 12. QSOP Third-Order Harmonic Distortion vs. Frequency for Various Temperatures vs. Frequency for Various Temperatures Rev. C | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE
04339-0-007
–80
04339-0-010
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 7. Second-Order Harmonic Distortion vs. Frequency Figure 10. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers for Various Output Powers
–40 –40 V V OUT = 61dBmV @ DEC 60 OUT = 61dBmV @ DEC 60 TA = +25°C T –50 A = +85°C –50 TA = –40°C –60 T T –60 A = –40°C A = +25°C DISTORTION (dBc) DISTORTION (dBc) –70 –70 TA = +85°C –80
04339-0-008
–80
04339-0-011
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 8. LFCSP Second-Order Harmonic Distortion Figure 11. LFCSP Third-Order Harmonic Distortion vs. Frequency for Various Temperatures vs. Frequency for Various Temperatures
–40 –40 V V OUT = 61dBmV @ DEC 60 OUT = 61dBmV @ DEC 60 TA = +25°C TA = +70°C –50 –50 TA = +25°C TA = –25°C –60 –60 TA = –25°C DISTORTION (dBc) DISTORTION (dBc) –70 –70 TA = +70°C –80
04339-0-009
–80
04339-0-012
5 15 25 35 45 55 65 5 15 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz)
Figure 9. QSOP Second-Order Harmonic Distortion Figure 12. QSOP Third-Order Harmonic Distortion vs. Frequency for Various Temperatures vs. Frequency for Various Temperatures Rev. C | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE