Datasheet AD640 (Analog Devices) - 7

AD640 CIRCUIT DESCRIPTION LOG OUT LOG COM
The AD640 uses five cascaded limiting amplifiers to approxi-
Q9 Q10
mate a logarithmic response to an input signal of wide dynamic
COMMON R3 R4
range and wide bandwidth. This type of logarithmic amplifier
Q1 75
V
75
V
SIG IN
has traditionally been assembled from several small scale ICs
Q2 SIG OUT
and numerous external components. The performance of these semidiscrete circuits is often unsatisfactory. In particular, the
R1 R2 85
V
85
V logarithmic slope and intercept (see FUNDAMENTALS OF
Q3 Q4 Q5 Q6 Q7 Q8
LOGARITHMIC CONVERSION) are usually not very stable in the presence of supply and temperature variations even after laborious and expensive individual calibration. The AD640
–VS 1.09mA 1.09mA 565
m
A 565
m
A 2.18mA
employs high precision analog circuit techniques to ensure sta-
PTAT PTAT PTAT
bility of scaling over wide variations in supply voltage and tem- Figure 16. Simplified Schematic of a Single AD640 Stage perature. Laser trimming, using ac stimuli and operating deviation or ripple in the transfer function of ± 0.15 dB from the conditions similar to those encountered in practice, provides fully ideal response when the input is either a dc voltage or a square calibrated logarithmic conversion. wave. The slope of the transfer function is unaffected by the Each of the amplifier/limiter stages in the AD640 has a small input waveform; however, the intercept and ripple are waveform signal voltage gain of 10 dB (×3.162) and a –3 dB bandwidth of dependent (see EFFECT OF WAVEFORM ON INTERCEPT). 350 MHz. Fully differential direct coupling is used throughout. The input will usually be an amplitude modulated sinusoidal This eliminates the many interstage coupling capacitors usually carrier. In these circumstances the output is a fluctuating current at required in ac applications, and simplifies low frequency signal twice the carrier frequency (because of the full wave detection) processing, for example, in audio and sonar systems. The whose average value is extracted by an external low-pass filter, AD640 is intended for use in demodulating applications. Each which recovers a logarithmic measure of the baseband signal. stage incorporates a detector (a full wave transconductance
Circuit Operation
rectifier) whose output current depends on the absolute value of With reference to Figure 16, the transconductance pair Q7, Q8 its input voltage. and load resistors R3 and R4 form a limiting amplifier having a Figure 16 is a simplified schematic of one stage of the AD640. small signal gain of 10 dB, set by the tail current of nominally All transistors in the basic cell operate at near zero collector to 2.18 mA at 27°C. This current is basically proportional to abso- base voltage and low bias currents, resulting in low levels of ther- lute temperature (PTAT) but includes additional current to mally induced distortion. These arise when power shifts from one compensate for finite beta and junction resistance. The limiting set of transistors to another during large input signals. Rapid output voltage is ± 180 mV at 27°C and is PTAT. Emitter fol- recovery is essential when a small signal immediately follows a lowers Q1 and Q2 raise the input resistance of the stage, provide large one. This low power operation also contributes signifi- level shifting to introduce collector bias for the gain stage and cantly to the excellent long-term calibration stability of the AD640. detectors, reduce offset drift by forming a thermally balanced The complete AD640, shown in Figure 17, includes two bias quad with Q7 and Q8 and generate the detector biasing across regulators. One determines the small signal gain of the amplifier resistors R1 and R2. stages; the other determines the logarithmic slope. These bias Transistors Q3 through Q6 form the full wave detector, whose regulators maintain a high degree of stability in the resulting output is buffered by the cascodes Q9 and Q10. For zero input function by compensating for potentially large uncertainties Q3 and Q5 conduct only a small amount (a total of about in transistor parameters, temperature and supply voltages. A 32 µA) of the 565 µA tail currents supplied to pairs Q3–Q4 and third biasing block is used to accurately control the logarithmic Q5–Q6. This “pedestal” current flows in output cascode Q9 to intercept. the LOG OUT node (Pin 14). When driven to the peak output By summing the signals at the output of the detectors, a good of the preceding stage, Q3 or Q5 (depending on signal polarity) approximation to a logarithmic transfer function can be achieved. conducts lost of the tail current, and the output rises to 532 µA. The lower the stage gain, the more accurate the approximation, The LOG OUT current has thus changed by 500 µA as the but more stages are then needed to cover a given dynamic input has changed from zero to its maximum value. Since the range. The choice of 10 dB results in a theoretical periodic detectors are spaced at 10 dB intervals, the output increases by
RG1 RG0 1k
V
1k
V
RG2 LOG OUT LOG COM 17 16 15 14 INTERCEPT POSITIONING BIAS 12 +V 13 S COM 18 ATN OUT 19 FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE FULL-WAVE DETECTOR DETECTOR DETECTOR DETECTOR DETECTOR SIG +IN 20 11 SIG +OUT 10dB 10dB 10dB 10dB 10dB SIG –IN 1 10 SIG –OUT AMPLIFIER/LIMITER ATN LO 2 AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER AMPLIFIER/LIMITER 27
V
ATN COM 3 9 BL2 30
V
270
V
ATN COM 4 5 6 GAIN BIAS REGULATOR 7 SLOPE BIAS REGULATOR 8 ITC ATN IN BL1 –VS
Figure 17. Block Diagram of the Complete AD640 REV. D –7– Document Outline AD640-SPECIFICATIONS DC Specifications AC Specifications Thermal Characteristics ABSOLUTE MAXIMUM RATINGS TYPICAL DC PERFORMANCE CHARACTERISTICS TYPICAL AC PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE