Datasheet AD8306 (Analog Devices) - 7

AD8306 PRODUCT OVERVIEW
differential current-mode outputs of all ten detectors stages are The AD8306 is built on an advanced dielectrically-isolated summed with equal weightings and converted to a single-sided complementary bipolar process using thin-film resistor technol- voltage by the output stage, generating the logarithmic (or RSSI) ogy for accurate scaling. It follows well-developed foundations output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is, proven over a period of some fifteen years, with constant refine- 400 mV per decade). The junction between the lower and upper ment. The backbone of the AD8306 (Figure 19) comprises a regions is seamless, and the logarithmic law-conformance is chain of six main amplifier/limiter stages, each having a gain of typically well within ±0.4 dB over the 80 dB range from –80 dBV 12.04 dB (×4) and small-signal –3 dB bandwidth of 850 MHz. to 0 dBV (–67 dBm to +13 dBm). The input interface at INHI and INLO (Pins 4 and 5) is fully The full-scale rise time of the RSSI output stage, which operates differential. Thus it may be driven from either single-sided or as a two-pole low-pass filter with a corner frequency of 3.5 MHz, balanced inputs, the latter being required at the very top end of is about 200 ns. A capacitor connected between FLTR (Pin 10) the dynamic range, where the total differential drive may be as and VLOG can be used to lower the corner frequency (see be- large as 4 V in amplitude. low). The output has a minimum level of about 0.34 V (corre- The first six stages, also used in developing the logarithmic sponding to a noise power of –78 dBm, or 17 dB above the RSSI output, are followed by a versatile programmable-output, nominal intercept of –95 dBm). This rather high baseline level and thus programmable-gain, final limiter section. Its open- ensures that the pulse response remains unimpaired at very low collector outputs are also fully differential, at LMHI and LMLO inputs. (Pins 12 and 13). This output stage provides a gain of 18 dB The maximum RSSI output depends on the supply voltage and when using equal valued load and bias setting resistors and the the load. An output of 2.34 V, that is, 20 mV/dB × (9 + 108) dB, is pin-to-pin output is used. The overall voltage gain is thus 90 dB. guaranteed when using a supply voltage of 4.5 V or greater and When using RLIM = RLOAD = 200 Ω, the additional current a load resistance of 50 Ω or higher, for a differential input of consumption in the limiter is approximately 2.8 mA, of which 9 dBV (a 4 V sine amplitude, using balanced drives). When 2 mA goes to the load. The ratio depends on RLIM (for example, using a 3 V supply, the maximum differential input may still be when 20 Ω, the efficiency is 90%), and the voltage at the pin as high as –3 dBV (1 V sine amplitude), and the corresponding LMDR is rather more than 400 mV, but the total load current RSSI output of 2.1 V, that is, 20 mV/dB × (–3 + 108) dB is also is accurately (400 mV)/RLIM. guaranteed. The rise and fall times of the hard-limited (essentially square- A fully-programmable output interface is provided for the hard- wave) voltage at the outputs are typically 0.6 ns, when driven by limited signal, permitting the user to establish the optimal output a sine wave input having an amplitude of 316 µV or greater, and current from its differential current-mode output. Its magnitude RLOAD = 50 Ω. The change in time-delay (“phase skew”) over is determined by the resistor RLIM placed between LMDR (Pin the input range –73 dBV (316 µV in amplitude, or –60 dBm in 9) and ground, across which a nominal bias voltage of ~400 mV 50 Ω) to –3 dBV (1 V or +10 dBm) is ±56 ps (±2° at 100 MHz). appears. Using RLIM = 200 Ω, this dc bias current, which is commutated alternately to the output pins, LMHI and LMLO,
SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB
by the signal, is 2 mA. (The total supply current is somewhat
INHI LMHI
higher).
12dB 12dB 12dB LIM INLO LMLO
These currents may readily be converted to voltage form by the
LADR ATTEN BIAS LMDR CTRL
inclusion of load resistors, which will typically range from a few
4
3
DET DET DET DET
tens of ohms at 400 MHz to as high as 2 kΩ in lower frequency
I–V VLOG
applications. Alternatively, a resonant load may be used to extract
TEN DETECTORS SPACED 12dB FLTR
the fundamental signal and modulation sidebands, minimizing the out-of-band noise. A transformer or impedance matching
GAIN BAND-GAP SLOPE INTERCEPT ENBL BIAS REFERENCE BIAS TEMP COMP
network may also be used at this output. The peak voltage swing down from the supply voltage may be 1.2 V, before the output Figure 19. Main Features of the AD8306 transistors go into saturation. (The Applications section provides The six main cells and their associated full-wave detectors, further information on the use of this interface). having a transconductance (gm) form, handle the lower part of The supply current for all sections except the limiter output the dynamic range. Biasing for these cells is provided by two stage, and with no load attached to the RSSI output, is nomi- references, one of which determines their gain, the other being a nally 16 mA at TA = 27°C, substantially independent of supply band-gap cell which determines the logarithmic slope, and sta- voltage. It varies in direct proportion to the absolute tempera- bilizes it against supply and temperature variations. A special ture (PTAT). The RSSI load current is simply the voltage at dc-offset-sensing cell (not shown in Figure 19) is placed at the VLOG divided by the load resistance (e.g., 2.4 mA max in a end of this main section, and used to null any residual offset at 1 kΩ load). The limiter supply current is 1.1 times that flowing the input, ensuring accurate response down to the noise floor. in RLIM. The AD8306 may be enabled/disabled by a CMOS- The first amplifier stage provides a short-circuited voltage-noise compatible level at ENBL (Pin 8). spectral-density of 1.07 nV/√Hz. In the following simplified interface diagrams, the components The last detector stage includes a modification to temperature- denoted with an uppercase “R” are thin-film resistors having a stabilize the log-intercept, which is accurately positioned so as very low temperature-coefficient of resistance and high linearity to make optimal use of the full output voltage range. Four fur- under large-signal conditions. Their absolute value is typically ther “top end” detectors are placed at 12.04 dB taps along a within ± 20%. Capacitors denoted using an uppercase “C” have passive attenuator, to handle the upper part of the range. The a typical tolerance of ± 15% and essentially zero temperature or REV. A –7–