Datasheet AD8310 (Analog Devices) - 5

AD8310 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INLO 1 8 INHI COMM AD8310 2 7 ENBL TOP VIEW OFLT 3 6 BFIN (Not to Scale) VOUT 4 5 VPOS
01084-002 Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2. 2 COMM Common Pin. Usually grounded. 3 OFLT Offset Filter Access. Nominally at about 1.75 V. 4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load. 5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current. 6 BFIN Buffer Input. Used to lower postdetection bandwidth. 7 ENBL CMOS Compatible Chip Enable. Active when high. 8 INHI Second of Two Balanced Inputs. Biased roughly to VPOS/2. Rev. F | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PROGRESSIVE COMPRESSION SLOPE AND INTERCEPT CALIBRATION OFFSET CONTROL PRODUCT OVERVIEW ENABLE INTERFACE INPUT INTERFACE OFFSET INTERFACE OUTPUT INTERFACE USING THE AD8310 BASIC CONNECTIONS TRANSFER FUNCTION IN TERMS OF SLOPE AND INTERCEPT dBV vs. dBm INPUT MATCHING NARROW-BAND MATCHING GENERAL MATCHING PROCEDURE Step 1: Tune Out CIN Step 2: Calculate CO and LO Step 3: Split CO into Two Parts Step 4: Calculate LM SLOPE AND INTERCEPT ADJUSTMENTS INCREASING THE SLOPE TO A FIXED VALUE OUTPUT FILTERING LOWERING THE HIGH-PASS CORNER FREQUENCY OF THE OFFSET COMPENSATION LOOP APPLICATIONS INFORMATION CABLE-DRIVING DC-COUPLED INPUT EVALUATION BOARD DIE INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE