Datasheet AD8319 (Analog Devices) - 10

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AD8319 Data Sheet THEORY OF OPERATION
The AD8319 is a five-stage demodulating logarithmic amplifier, The logarithmic function is approximated in a piecewise fashion specifically designed for use in RF measurement and power control by five cascaded gain stages. (For a detailed explanation of the applications at frequencies up to 10 GHz. A block diagram is logarithm approximation, refer to the AD8307 data sheet.) The shown in Figure 21. Sharing much of its design with the AD8318 cells have a nominal voltage gain of 9 dB each and a 3 dB logarithmic detector/controller, the AD8319 maintains tight bandwidth of 10.5 GHz. Using precision biasing, the gain is intercept variability vs. temperature over a 40 dB range. Additional stabilized over temperature and supply variations. The overall enhancements over the AD8318, such as reduced RF burst dc gain is high due to the cascaded nature of the gain stages. response time of 6 ns to 10 ns, 22 mA supply current, and An offset compensation loop is included to correct for offsets board space requirements of only 2 mm × 3 mm add to the low within the cascaded cells. At the output of each of the gain cost and high performance benefits found in the AD8319. stages, a square-law detector cell is used to rectify the signal.
VPSO TADJ
The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level.
GAIN
Along with the five gain stages and detector cells, an additional
BIAS SLOPE V I VSET
detector is included at the input of the AD8319, providing a 40 dB dynamic range in total. After the detector currents are
I V VOUT
summed and filtered, the following function is formed at the
DET DET DET DET CLPF
summing node:
INHI
ID × log10(VIN/VINTERCEPT) (1)
INLO
21 where: 0 5-
COMM
570 I 0 D is the internally set detector current. Figure 21. Block Diagram VIN is the input signal voltage. V A fully differential design, using a proprietary, high speed INTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V). SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB log conformance error is typically 0 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8319 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMM, provides a quality low impedance connection to the PCB ground. The package paddle, which is internally connected to the COMM pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB. Rev. D | Page 10 of 19 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8319 BASIC CONNECTIONS INPUT SIGNAL COUPLING OUTPUT INTERFACE SETPOINT INTERFACE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE MEASUREMENT MODE SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE CONTROLLER MODE OUTPUT FILTERING OPERATION BEYOND 8 GHz EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE