Datasheet ADRF5545A (Analog Devices) - 6

ADRF5545A Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS -CHA CHA CHA ND C ND ND ND C C G TERM NI G G G VDD1- NI NI VDD2- 40 39 38 37 36 35 34 33 32 31 GND 1 30 GND GND 2 29 RXOUT-CHA ANT-CHA 3 28 GND GND 4 27 BP-CHA SWCTRL-CHAB 5 ADRF5545A 26 PD-CHAB SWVDD-CHAB 6 TOP VIEW 25 NIC GND 7 (Not to Scale) 24 BP-CHB ANT-CHB 8 23 GND GND 9 22 RXOUT-CHB GND 10 21 GND 11 12 13 14 15 16 17 18 19 20 ND C ND ND ND C C G NI NI NI -CHB G G G CHB CHB VDD1- VDD2- NOTES TERM 1. NIC = NOT INTERNALLY CONNECTED. IT IS RECOMMENDED TO CONNECT NIC TO THE RF GROUND OF THE PCB.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF OR DC GROUND.
20051- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 2, 4, 7, 9 to 11, 14 to 16, 21, 23, GND Ground. 28, 30, 35 to 37, 40 3 ANT-CHA RF Input to Channel A. 5 SWCTRL-CHAB Control Voltage for Switches on Channel A and Channel B. 6 SWVDD-CHAB Supply Voltage for Switches on Channel A and Channel B. 8 ANT-CHB RF Input to Channel B. 12 TERM-CHB Termination Output for Channel B. This pin is the transmitter path for Channel B. 13, 18, 19, 25, 32, 33, 38 NIC Not Internally Connected. It is recommended to connect NIC to the RF ground of the PCB. 17 VDD1-CHB Supply Voltage for Stage 1 LNA on Channel B. 20 VDD2-CHB Supply Voltage for Stage 2 LNA on Channel B. 22 RXOUT-CHB RF Output. This pin is the receiver path for Channel B. 24 BP-CHB Bypass Second Stage LNA of Channel B. 26 PD-CHAB Power-Down All Stages of LNA for Channel A and Channel B. 27 BP-CHA Bypass Second Stage LNA of Channel A. 29 RXOUT-CHA RF Output. This pin is the receiver path for Channel A. 31 VDD2-CHA Supply Voltage for Stage 2 LNA on Channel A. 34 VDD1-CHA Supply Voltage for Stage 1 LNA on Channel A. 39 TERM-CHA Termination Output for Channel A. This pin is the transmitter path for Channel A. EPAD Exposed Pad. The exposed pad must be connected to RF or dc ground. Rev. B | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS 2.6 GHZ TUNED OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION RECEIVE OPERATION, HIGH GAIN MODE WITH 2.6 GHZ TUNING RECEIVE OPERATION, LOW GAIN MODE WITH 2.6 GHz TUNING TRANSMIT OPERATION AT WITH 2.6 GHz TUNING THEORY OF OPERATION SIGNAL PATH SELECT Transmit Operation Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION 2.6 GHZ OPERATION OUTLINE DIMENSIONS ORDERING GUIDE