Datasheet HMC1099 (Analog Devices) - 3

Data Sheet HMC1099 SPECIFICATIONS ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.01 GHz to 0.4 GHz.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 0.01 0.4 GHz GAIN Small Signal Gain 18 20 dB Gain Flatness ±1 dB RETURN LOSS Input 12 dB Output 15 dB POWER Output Power for 4 dB Compression P4dB 40 dBm Power Gain for P4dB Compression 15 dB Saturated Output Power PSAT 40.5 dBm >10 W saturated output power Power Gain for PSAT 13 dB Power Added Efficiency PAE 73 % OUTPUT THIRD-ORDER INTERCEPT IP3 49 dBm Measurement taken at POUT/tone = 30 dBm NOISE FIGURE 8 dB TOTAL SUPPLY CURRENT IDD 100 mA Adjust the gate bias control voltage (VGG) between −8 V to 0 V to achieve an IDD = 100 mA typical TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.4 GHz to 0.7 GHz.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 0.4 0.7 GHz GAIN Small Signal Gain 16.5 18.5 dB Gain Flatness ±0.25 dB RETURN LOSS Input 9.5 dB Output 14 dB POWER Output Power for 4 dB Compression P4dB 40.5 dBm Power Gain for P4dB Compression 14 dB Saturated Output Power PSAT 40.5 dBm >10 W saturated output power Power Gain for PSAT 13 dB Power Added Efficiency PAE 69 % OUTPUT THIRD-ORDER INTERCEPT IP3 48 dBm Measurement taken at POUT/tone = 30 dBm NOISE FIGURE 5.5 dB TOTAL SUPPLY CURRENT IDD 100 mA Adjust the gate bias control voltage (VGG) between −8 V to 0 V to achieve an IDD = 100 mA typical Rev. A | Page 3 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL SUPPLY CURRENT BY VDD ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE