Datasheet HMC8500PM5E (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 10 W (40 dBm), 0.01 GHz to 2.8 GHz, GaN Power Amplifier |
| Páginas / Página | 17 / 6 — HMC8500PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 308 Kb |
| Idioma del documento | Inglés |
HMC8500PM5E. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GND 1. 24 GND. NIC 2. 23 NIC. NIC 3. 22 NIC. RFIN/V. 21 RFOUT/V
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 6 link to page 15 link to page 6 link to page 15 link to page 6
HMC8500PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C C ND ND G NI NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 HMC8500PM5E 22 NIC RFIN/V 4 GG 21 RFOUT/V TOP VIEW DD RFIN/V 5 GG (Not to Scale) 20 RFOUT/VDD NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND PACKAGE 9 10 11 12 13 14 15 16 BASE C C C C C C ND NI NI NI NI NI NI ND G G NOTES 1. NO INTERNAL CONNECTION. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA IS MEASURED WITH THESE PINS CONNECTED TO RF OR DC GROUND EXTERNALLY.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF OR DC GROUND.
16825- Figure 2. Pin Configuration
Table 6. Pad Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF or dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data is measured with 19, 22, 23, 26 to 31 these pins connected to RF or dc ground externally. 4, 5 RFIN/V RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/V pin is dc-coupled GG GG with internal prematching and requires external matching to 50 Ω, as shown in Figure 44. See Figure 4 for the RFIN/V interface schematic. GG 20, 21 RFOUT/V RF Output/Drain Bias Voltage. This is a multifunction pin. The RFOUT/V pin is dc-coupled and requires DD DD external matching to 50 Ω, as shown in Figure 44. See Figure 4 for the RFOUT/V interface schematic. DD EPAD Exposed Pad. The exposed pad must be connected to RF or dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 16825- 16825- Figure 3. GND Interface Schematic Figure 4. RFIN/VGG and RFOUT/VDD Interface Schematic Rev. A | Page 6 of 17 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Total Supply Current by VDD Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Evaluation Board Outline Dimensions Ordering Guide
HMC8500PM5E Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C C C C C C ND ND G NI NI NI NI NI NI G 32 31 30 29 28 27 26 25 GND 1 24 GND NIC 2 23 NIC NIC 3 HMC8500PM5E 22 NIC RFIN/V 4 GG 21 RFOUT/V TOP VIEW DD RFIN/V 5 GG (Not to Scale) 20 RFOUT/VDD NIC 6 19 NIC NIC 7 18 NIC GND 8 17 GND PACKAGE 9 10 11 12 13 14 15 16 BASE C C C C C C ND NI NI NI NI NI NI ND G G NOTES 1. NO INTERNAL CONNECTION. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA IS MEASURED WITH THESE PINS CONNECTED TO RF OR DC GROUND EXTERNALLY.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF OR DC GROUND.
16825- Figure 2. Pin Configuration
Table 6. Pad Function Descriptions Pin No. Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32 GND Ground. These pins must be connected to RF or dc ground. See Figure 3 for the GND interface schematic. 2, 3, 6, 7, 10 to 15, 18, NIC No Internal Connection. These pins are not connected internally. However, all data is measured with 19, 22, 23, 26 to 31 these pins connected to RF or dc ground externally. 4, 5 RFIN/V RF Input/Gate Bias Control Voltage. This pin is a multifunction pin. The RFIN/V pin is dc-coupled GG GG with internal prematching and requires external matching to 50 Ω, as shown in Figure 44. See Figure 4 for the RFIN/V interface schematic. GG 20, 21 RFOUT/V RF Output/Drain Bias Voltage. This is a multifunction pin. The RFOUT/V pin is dc-coupled and requires DD DD external matching to 50 Ω, as shown in Figure 44. See Figure 4 for the RFOUT/V interface schematic. DD EPAD Exposed Pad. The exposed pad must be connected to RF or dc ground.
INTERFACE SCHEMATICS RFOUT/VDD GND
003
RFIN/VGG
004 16825- 16825- Figure 3. GND Interface Schematic Figure 4. RFIN/VGG and RFOUT/VDD Interface Schematic Rev. A | Page 6 of 17 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Total Supply Current by VDD Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Evaluation Board Outline Dimensions Ordering Guide