Datasheet HMC8205BF10 (Analog Devices) - 5

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Data Sheet HMC8205BF10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 HMC8205BF10 10 VDD2 NC VDD2 NC 2 9 3 8 RFIN RFOUT 4 7 NC VGG1 NC VDD1 5 6 PACKAGE BASE GND
101 13790- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1, 2 VDD2 Drain Bias for Second Stage of Amplifier. See Figure 3 for the VDD2 interface schematic. 3 RFIN RF Input (RFIN). It is ac-coupled and internally matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 4, 5, 9, 10 NC No Internal Connection. 6 VDD1 Drain Bias for First Stage of Amplifier. See Figure 5 for the VDD1 interface schematic. 7 VGG1 Gate Control for Second Stage of Amplifier. See Figure 6 for the VGG1 interface schematic. 8 RFOUT RF Output (RFOUT). It is ac-coupled and internally matched to 50 Ω. See Figure 7 for the RFOUT interface schematic. Package Base GND Package Base. The package base must be connected to RF/dc ground. See Figure 8 for the GND Interface schematic.
INTERFACE SCHEMATICS VDD2
002 004 13790-
VGG1
13790- Figure 3. VDD2 Interface Figure 6. VGG1 Interface 003 006
RFIN RFOUT
13790- 13790- Figure 4. RFIN Interface Figure 7. RFOUT Interface
VDD1 GND
007 13790- 005 13790- Figure 5. VDD1 Interface Figure 8. GND Interface Rev. C | Page 5 of 14 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Application Circuit Evaluation PCB Outline Dimensions Ordering Guide