Datasheet HMC8415LP6GE (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 40 W (46 dBm), 9 GHz to 10.5 GHz, GaN Power Amplifier |
| Páginas / Página | 23 / 6 — HMC8415LP6GE. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 518 Kb |
| Idioma del documento | Inglés |
HMC8415LP6GE. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. GG2. GG3. DD1. DD2. DD3. 40 39 38 37 36 35 34 33 32 31. NIC 1
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HMC8415LP6GE Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A A A A A C C C GG1 GG2 GG3 DD1 DD2 DD3 DD3 V V V NI V V NI NI V V 40 39 38 37 36 35 34 33 32 31 NIC 1 30 NIC NIC 2 29 NIC NIC 3 28 NIC GND 4 27 GND RFIN 5 HMC8415LP6GE 26 RFOUT GND 6 TOP VIEW 25 GND (Not to Scale) NIC 7 24 NIC NIC 8 23 NIC NIC 9 22 NIC NIC 10 21 NIC 11 12 13 14 15 16 17 18 19 20 B B B C B B C C B B NI NI NI GG1 GG2 GG3 DD1 DD2 DD3 DD3 V V V V V V V NOTES 1. NIC = NO INTERNAL CONNECTION.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
16688- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 to 3, 7 to 10, 14, 17, 18, 21 to 24, NIC No Internal Connection. These pins must be connected to RF and dc ground. 28 to 30, 33, 34, 37 4, 6, 25, 27 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 5 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 11 to13, 38 to 40 VGG1B, VGG2B, VGG3B, Gate Control Voltage Pins. External bypass capacitors of 1 µF, 100 pF, and 2.2 nF are VGG1A, VGG2A, VGG3A required. See Figure 5 for the VGG1B, VGG2B, VGG3B, VGG1A, VGG2A, and VGG3A interface schematic. 15, 16, 19, 20, 31, 32, 35, 36 VDD1B, VDD2B, VDD3B, Drain Bias Pins for the Amplifier. External bypass capacitors of 1 nF and 3.3 Ω VDD1A, VDD2A, VDD3A resistors are required. See Figure 7 for the VDD1B, VDD2B, VDD3B, VDD1A, VDD2A, and VDD3A interface schematic. 26 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. Rev. A | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL TARGET QUIESCENT CURRENT BY VDDxA/VDDxB ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT AND PULSOR CIRCUIT USING THE EV1HMC8415LP6G WITH THE DRAIN BIAS PULS0R BOARD RECOMMENDED BIAS SEQUENCE Power-Up Bias Concept for the EV1HMC8415LP6G with the Pulsor Power-Down Bias Concept for the EV1HMC8415LP6G with the Pulsor MAKING AVERAGE TO PULSED APPROXIMATIONS EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
HMC8415LP6GE Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A A A A A C C C GG1 GG2 GG3 DD1 DD2 DD3 DD3 V V V NI V V NI NI V V 40 39 38 37 36 35 34 33 32 31 NIC 1 30 NIC NIC 2 29 NIC NIC 3 28 NIC GND 4 27 GND RFIN 5 HMC8415LP6GE 26 RFOUT GND 6 TOP VIEW 25 GND (Not to Scale) NIC 7 24 NIC NIC 8 23 NIC NIC 9 22 NIC NIC 10 21 NIC 11 12 13 14 15 16 17 18 19 20 B B B C B B C C B B NI NI NI GG1 GG2 GG3 DD1 DD2 DD3 DD3 V V V V V V V NOTES 1. NIC = NO INTERNAL CONNECTION.
002
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
16688- Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 to 3, 7 to 10, 14, 17, 18, 21 to 24, NIC No Internal Connection. These pins must be connected to RF and dc ground. 28 to 30, 33, 34, 37 4, 6, 25, 27 GND Ground. These pins must be connected to RF and dc ground. See Figure 3 for the GND interface schematic. 5 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the RFIN interface schematic. 11 to13, 38 to 40 VGG1B, VGG2B, VGG3B, Gate Control Voltage Pins. External bypass capacitors of 1 µF, 100 pF, and 2.2 nF are VGG1A, VGG2A, VGG3A required. See Figure 5 for the VGG1B, VGG2B, VGG3B, VGG1A, VGG2A, and VGG3A interface schematic. 15, 16, 19, 20, 31, 32, 35, 36 VDD1B, VDD2B, VDD3B, Drain Bias Pins for the Amplifier. External bypass capacitors of 1 nF and 3.3 Ω VDD1A, VDD2A, VDD3A resistors are required. See Figure 7 for the VDD1B, VDD2B, VDD3B, VDD1A, VDD2A, and VDD3A interface schematic. 26 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground. Rev. A | Page 6 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL TARGET QUIESCENT CURRENT BY VDDxA/VDDxB ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT AND PULSOR CIRCUIT USING THE EV1HMC8415LP6G WITH THE DRAIN BIAS PULS0R BOARD RECOMMENDED BIAS SEQUENCE Power-Up Bias Concept for the EV1HMC8415LP6G with the Pulsor Power-Down Bias Concept for the EV1HMC8415LP6G with the Pulsor MAKING AVERAGE TO PULSED APPROXIMATIONS EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE