Datasheet ADTR1107 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 6 GHz to 18 GHz, Front-End IC |
| Páginas / Página | 28 / 7 — Data Sheet. ADTR1107. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. _S L. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 943 Kb |
| Idioma del documento | Inglés |
Data Sheet. ADTR1107. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. _S L. DD_L. GG_. DD_S. GND 1. GND. RX_OUT. ANT. TOP VIEW. GND 4
Línea de modelo para esta hoja de datos
Versión de texto del documento
Data Sheet ADTR1107 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A W N N W L SW _S L D S_ R DD_L GG_ DD_S V V GN VS CT V 4 3 2 1 0 9 2 2 2 2 2 1 GND 1 18 GND RX_OUT 2 17 ANT GND ADTR1107 3 16 GND TOP VIEW GND 4 15 GND (Not to Scale) TX_IN 5 14 GND GND 6 13 GND 7 8 9 01 11 21 A C C D UT _PA NI NI G GN _O DD_P R VG V L CP NOTES 1. NIC = NO INTERNAL CONNECTION. SOLDER THESE PINS TO A LOW IMPEDANCE GROUND PLANE.
2 00
2. EXPOSED PAD. MUST BE CONNECTED
6-
TO RF/DC GROUND.
2214 Figure 2. Pin Configuration
Table 9. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 4, 6, 11, 13 GND Ground. Solder these pins to a low impedance ground plane. to 16, 18, 22 2 RX_OUT Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω. 5 TX_IN Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω. 7 VGG_PA Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier. 8 VDD_PA Power Amplifier Drain Bias Voltage. 9, 10 NIC No Internal Connection. Solder these pins to a low impedance ground plane. 12 CPLR_OUT Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power. 17 ANT RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. 19 VDD_SW SPDT Switch Positive Bias Voltage. 20 CTRL_SW Switch Digital Control. This pin controls the state of the SPDT switch. 21 VSS_SW SPDT Switch Negative Bias Voltage. 23 VGG_LNA LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA. 24 VDD_LNA LNA Drain Voltage Bias. EPAD Exposed Pad. Must be connected to RF/dc ground. Rev. A | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS TRANSMIT STATE RECEIVE STATE THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING TYPICAL APPLICATION CIRCUIT INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER OUTLINE DIMENSIONS ORDERING GUIDE
2 00
2. EXPOSED PAD. MUST BE CONNECTED
6-
TO RF/DC GROUND.
2214 Figure 2. Pin Configuration
Table 9. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 4, 6, 11, 13 GND Ground. Solder these pins to a low impedance ground plane. to 16, 18, 22 2 RX_OUT Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω. 5 TX_IN Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω. 7 VGG_PA Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier. 8 VDD_PA Power Amplifier Drain Bias Voltage. 9, 10 NIC No Internal Connection. Solder these pins to a low impedance ground plane. 12 CPLR_OUT Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power. 17 ANT RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. 19 VDD_SW SPDT Switch Positive Bias Voltage. 20 CTRL_SW Switch Digital Control. This pin controls the state of the SPDT switch. 21 VSS_SW SPDT Switch Negative Bias Voltage. 23 VGG_LNA LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA. 24 VDD_LNA LNA Drain Voltage Bias. EPAD Exposed Pad. Must be connected to RF/dc ground. Rev. A | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS TRANSMIT STATE RECEIVE STATE THEORY OF OPERATION APPLICATIONS INFORMATION RECOMMENDED BIAS SEQUENCING TYPICAL APPLICATION CIRCUIT INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER OUTLINE DIMENSIONS ORDERING GUIDE