ADPA7005CHIPData SheetABSOLUTE MAXIMUM RATINGS Table 3.THERMAL RESISTANCEParameterRating Thermal performance is directly linked to system design and Drain Bias Voltage (VDDx) 6.0 V operating environment. Careful attention to the printed circuit VGG1 −1.5 to 0 V board (PCB) thermal design is required. θJC is the channel to Radio Frequency Input Power (RFIN) 27 dBm case thermal resistance, channel to bottom of die using die Continuous Power Dissipation (PDISS), 13.4 W attach epoxy. T = 85°C (Derate 149.2 mW/°C Above 85°C) Table 4. Thermal Resistance Storage Temperature Range −65°C to +150°C Package TypeθJCUnit Operating Temperature Range −55°C to +85°C C-12-3 6.7 °C/W Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Class 1B (passed Table 5. Reliability Information 500 V) ParameterTemperature (°C) Stresses at or above those listed under Absolute Maximum Junction Temperature to Maintain 175 Ratings may cause permanent damage to the product. This is a 1,000,000 Hour Mean Time to Failure stress rating only; functional operation of the product at these (MTTF) or any other conditions above those indicated in the operational Nominal Junction Temperature (T = 85°C, 125.2 V section of this specification is not implied. Operation beyond DD = 5 V, IDQ = 600 mA) the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0 | Page 4 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTIC CONSTANT IDD OPERATION THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding BIASING ADPA7005CHIP WITH THE HMC980LP4E APPLICATION CIRCUIT SETUP LIMITING VGATE FOR ADPA7005CHIP VGGx ABSOLUTE MAXIMUM RATING REQUIREMENT HMC980LP4E BIAS SEQUENCE Power-Up Sequence Power-Down Sequence CONSTANT DRAIN CURRENT BIASING vs. CONSTANT GATE VOLTAGE BIASING TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE