Datasheet ADL5523 (Analog Devices)

400 MHz to 4000 MHz Low Noise Amplifier Data Sheet ADL5523 FEATURES FUNCTIONAL BLOCK DIAGRAM Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz VBIAS ACTIVE 1 8 VPOS BIAS Requires few external components RFIN 2 7 RFOUT Integrated active bias control circuit NC 3 6 NC Integrated dc blocking capacitors ADL5523 Adjustable bias for low power applications NC 4 5 NC
01 0 9-
Single-supply operation from 3 V to 5 V NC = NO CONNECT
82 06
Gain of 21.5 dB at 900 MHz
Figure 1.
OIP3 of 34.0 dBm at 900 MHz P1dB of 21.0 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 20.8 dB gain available GENERAL DESCRIPTION
The ADL5523 is a high performance GaAs pHEMT low noise The ADL5523 is easy to tune, requiring only a few external amplifier. It provides high gain and low noise figure for single- components. The device can support operation from 3 V to 5 V, downconversion IF sampling receiver architectures as well as and the current draw can be adjusted with the external bias direct-downconversion receivers. resistor for applications requiring very low power consumption. The ADL5523 provides a high level of integration by incorporating The ADL5523 comes in a compact, thermally enhanced, 3 mm × the active bias and the dc blocking capacitors, making it very 3 mm LFCSP and operates over the temperature range of −40°C easy to use while not sacrificing design flexibility. to +85C. A fully populated evaluation board is also available.
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Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DC SPECIFICATIONS DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 900 MHz, VPOS = 5 V 1950 MHZ, VPOS = 5 V 2600 MHz, VPOS = 5 V 3500 MHz, VPOS = 5 V 900 MHz, VPOS = 3 V 1950 MHz, VPOS = 3 V 2600 MHz, VPOS = 3 V 3500 MHz, VPOS = 3 V DC CHARACTERISTICS BASIC CONNECTIONS EVALUATION BOARD SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN TUNING THE ADL5523 FOR OPTIMAL NOISE FIGURE TUNING S22 TUNING THE LNA INPUT FOR OPTIMAL GAIN TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE S11 OF THE LNA WITH S22 MATCHED OUTLINE DIMENSIONS ORDERING GUIDE