Datasheet ADL7003 (Analog Devices) - 6

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ADL7003 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 3 4 5 6 7 1A 2A 3A 4A 12A 34A DD DD DD DD GG V V GG V V V V RFOUT 8 ADL7003 TOP VIEW (Not to Scale) 1 RFIN 12B 1B 2B 34B 3B 4B GG DD DD GG DD DD V V V V V V 14 13 12 11 10 9
002 15691- Figure 2. Pad Configuration
Table 6. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2 VGG12A Gate Control Pad for the First and Second Stage Amplifiers. See Figure 4 for the interface schematic. V Drain Bias Voltage Pads for the First and Second Stage Amplifiers. External bypass capacitors of 120 pF, 0.1 µF, 3, 4 DD1A, VDD2A and 4.7 µF are required. Connect these pads to a 3 V supply. See Figure 5 for the interface schematic. 5 VGG34A Gate Control Pad for the Third and Fourth Stage Amplifiers. See Figure 4 for the interface schematic. V Drain Bias Voltage Pads for the Third and Fourth Stage Amplifiers. External bypass capacitors of 120 pF, 0.1 µF, 6, 7 DD3A, VDD4A and 4.7 µF are required. Connect these pads to a 3 V supply. See Figure 5 for the interface schematic. 8 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic. V Drain Bias Voltage Pads for the Fourth and Third Stage Alternative Bias Configuration. External bypass 9, 10 DD4B, VDD3B capacitors of 120 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic. Gate Control Pad for the Third and Fourth Stage Alternative Bias Configuration. Coupling capacitors are 11 VGG34B required. See Figure 8 for the interface schematic. V Drain Bias Voltage Pads for the Second and First Stage Alternative Bias Configuration. External bypass 12, 13 DD2B, VDD1B capacitors of 120 pF, 0.1 µF, and 4.7 µF are required. See Figure 7 for the interface schematic. Gate Control Pad for the First and Second Stage Alternative Bias Configuration. Coupling capacitors are 14 VGG12B required. See Figure 8 for the interface schematic. Die Bottom GND Ground. Die bottom must be connected to RF/dc ground. See Figure 6 for the interface schematic. Rev. 0 | Page 6 of 18 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 50 GHz TO 70 GHz FREQUENCY RANGE 70 GHz TO 90 GHz FREQUENCY RANGE 90 GHz TO 95 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATIC TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE