Datasheet HMC5805ALS6 (Analog Devices) - 8

HMC5805ALS6
v02.0517
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER DC - 40 GHz Application Information
BIASING PROCEDURES: DC bias must be applied to the drain via an RF choke/inductor connection to the RFOUT/VDD pin. Gate bias must be applied to VGG1 and VGG2. Capacitive bypassing is recommended for all of the DC bias pins and AC terminations to ground are recom- mended for ACG1-ACG4, as shown in the Application Circuit. T M The recommended bias sequence during power-up is as follows: 1. Set VGG1 to −2.0 V to pinch off the channels of the lower FETs. 2. Set VDD to 10.0 V. Because the lower FETs are pinched off, IDQ remains very low upon application of VDD. R - S 3. Set VGG2 to 3.5 V. E 3. Adjust VGG1 to be more positive until a quiescent drain current of 175 mA has been obtained. W 4. Apply the RF input signal. O The recommended bias sequence during power-down is as follows: 1. Turn off the RF input signal. 2. Set VGG1 to −2.0 V to pinch off the channels of the lower FETs. R & P 3. Set VGG2 to 0 V. A 4. Set VDD to 0 V. E 5. Set VGG1 to 0 V. IN Power-up and power-down sequences may differ from the ones described, though care must always be taken to ensure adherence to the values shown in the Absolute Maximum Ratings. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit as config- S - L ured on our evaluation board. The bias conditions shown in the specifications section are the operating points recom- R mended to optimize the overal performance. Operation using other bias conditions may provide performance that IE differs from what is shown in this data sheet.
Application Circuit
LIF P M A NOTE 1: Drain Bias (Vdd) must be applied through a broadband bias tee with low series resistance and capable of providing 250 mA For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D
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Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Gain & Return Loss Gain vs. Temperature Input Return Loss vs. Temperature Output Return Loss vs. Temperature P1dB vs. Temperature Psat vs. Temperature Psat vs. Supply Voltage P1dB vs. Supply Current Psat vs. Supply Current Output IP3 vs. Temperature @ Pout = 14 dBm / Tone Output IP3 vs. Supply Voltage @ Pout = 14 dBm / Tone Output IP3 vs. Supply Currents @ Pout = 14 dBm / Tone Output IM3 @ Vdd = +10V Output IM3 @ Vdd = +11V Reverse Isolation vs. Temperature Power Compression @ 20 GHz Absolute Maximum Ratings Outline Drawing Pad Descriptions Application Circuit