Datasheet AD712 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Precision, Low Cost, High Speed, BiFET Dual Op Amp |
| Páginas / Página | 20 / 8 — AD712. Data Sheet. 100. –70. VS = ±15V. VCM = 1V p-p. –80. 25°C. 3V rms … |
| Revisión | I |
| Formato / tamaño de archivo | PDF / 569 Kb |
| Idioma del documento | Inglés |
AD712. Data Sheet. 100. –70. VS = ±15V. VCM = 1V p-p. –80. 25°C. 3V rms RL = 2kΩ. –90. CL = 100pF. B) d. R (. D ( –100. –110. –120. –130. 10k. 100k
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AD712 Data Sheet 100 –70 VS = ±15V VCM = 1V p-p –80 80 25°C 3V rms RL = 2kΩ –90 CL = 100pF 60 B) d B) d R ( D ( –100 H CM T 40 –110 20 –120 0 –130 10 100 1k 10k 100k 1M
14 17 0
100 1k 10k 100k
0 3- 3-
FREQUENCY (Hz)
82
FREQUENCY (Hz)
82 00 00 Figure 14. Common-Mode Rejection vs. Frequency Figure 17. Total Harmonic Distortion vs. Frequency
30 1k RL = 2kΩ 25°C 25 VS = ±15V ) p-p) V √Hz V/ G ( 20 100 IN E (n W S AG E T G 15 L A VO LT E O IS V T 10 10 U NO T TP U P OU 5 IN 0 1
18
100k 1M 10M
15 0
1 10 100 1k 10k 100k
-0 3- 23
FREQUENCY (Hz)
82
FREQUENCY (Hz)
08 00 0 Figure 15. Large Signal Frequency Response Figure 18. Input Noise Voltage Spectral Density
10 25 8 OLTS 6 20 V 4 TO ± s) V µ 0 2 V/ 15 1% 0.1% 0.01% OM E ( 0 T A ERROR 1% 0.1% 0.01% G FR R –2 IN 10 EW W S –4 SL T U TP –6 5 OU –8 –10 0 0.5 0.6 0.7 0.8 0.9 1.0
-016
0 100 200 300 400 500 600 700 800 900
9
SETTLING TIME (µs)
823
INPUT ERROR SIGNAL (mV)
-01 00 23
(AT SUMMING JUNCTION)
008 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. I | Page 8 of 20 Document Outline FEATURES CONNECTION DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS SETTLING TIME OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL APPLICATIONS INFORMATION GUARDING DAC CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN ADC DRIVING A LARGE CAPACITIVE LOAD FILTERS ACTIVE FILTER APPLICATIONS SECOND-ORDER LOW-PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS ORDERING GUIDE
14 17 0
100 1k 10k 100k
0 3- 3-
FREQUENCY (Hz)
82
FREQUENCY (Hz)
82 00 00 Figure 14. Common-Mode Rejection vs. Frequency Figure 17. Total Harmonic Distortion vs. Frequency
30 1k RL = 2kΩ 25°C 25 VS = ±15V ) p-p) V √Hz V/ G ( 20 100 IN E (n W S AG E T G 15 L A VO LT E O IS V T 10 10 U NO T TP U P OU 5 IN 0 1
18
100k 1M 10M
15 0
1 10 100 1k 10k 100k
-0 3- 23
FREQUENCY (Hz)
82
FREQUENCY (Hz)
08 00 0 Figure 15. Large Signal Frequency Response Figure 18. Input Noise Voltage Spectral Density
10 25 8 OLTS 6 20 V 4 TO ± s) V µ 0 2 V/ 15 1% 0.1% 0.01% OM E ( 0 T A ERROR 1% 0.1% 0.01% G FR R –2 IN 10 EW W S –4 SL T U TP –6 5 OU –8 –10 0 0.5 0.6 0.7 0.8 0.9 1.0
-016
0 100 200 300 400 500 600 700 800 900
9
SETTLING TIME (µs)
823
INPUT ERROR SIGNAL (mV)
-01 00 23
(AT SUMMING JUNCTION)
008 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. I | Page 8 of 20 Document Outline FEATURES CONNECTION DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS SETTLING TIME OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL APPLICATIONS INFORMATION GUARDING DAC CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN ADC DRIVING A LARGE CAPACITIVE LOAD FILTERS ACTIVE FILTER APPLICATIONS SECOND-ORDER LOW-PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS ORDERING GUIDE