Datasheet AD744 (Analog Devices) - 10

AD744 BIPOLAR OFFSET ADJUST VCC 0.1
␮
F 100
⍀
REF OUT GAIN ADJUST 20V SPAN 100
⍀
10V C AD565A 5k
⍀
LEAD REF 10V SPAN +15V 19.95k
⍀
9.96k
⍀
10pF IN 1
␮
F 5k
⍀
DAC OUT REF GND 20k
⍀
8k
⍀
AD744 1
␮
F 0.1
␮
F POWER –15V GND MSB LSB –VEE
Figure 34. ±10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AND TECHNIQUES AMPLIFIER CIRCUIT
The instrumentation amplifier circuit shown in Figure 36 can
DAC Buffers (I-to-V Converters)
Digital-to-analog converters which use bipolar transistors to provide a range of gains from unity up to 1000 and higher. The switch currents into (or out of) their outputs can achieve very circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain fast settling times. The AD565A, for example, is specified to of 10; settling time for the entire circuit is less than 2 µs settle to 12 bits in less than 250 ns, with a current output. How- to within 0.01% for a 10 V step, (G = 10). ever, in many applications, a voltage output is desirable, and it While the AD744 is not stable with 100% negative feedback (as would be useful – perhaps essential – that this I-to-V conversion when connected as a standard voltage follower), phase margin be accomplished without increasing the settling time or without and therefore stability at unity gain may be increased to an accept- degrading the accuracy of the DAC. able level by placing the parallel combination of a resistor and a Figure 34 is a schematic of an AD565A DAC using an AD744 small lead capacitor between each amplifier’s output and its output buffer. The 10 pF C inverting input terminal. LEAD capacitor compensates for the DAC’s output capacitance, plus the 5.5 pF amplifier input The only penalty associated with this method is a small band- capacitance. width reduction at low gains. The optimum value for CLEAD Figure 35 is an oscilloscope photo of the AD744’s output volt- may be determined from the graph of Figure 41. This technique age with a +10 V to 0 V step applied; this corresponds to an all can be used in the circuit of Figure 36 to achieve stable opera- “1s” to all “0s” code change on the DAC. Since the DAC is tion at gains from unity to over 1000.
20,000 CIRCUIT GAIN = + 1 RG AD744 –IN *1.5pF – 20pF (TRIM FOR BEST SETTLING TIME) A1 10k
⍀
**10k
⍀
7.5pF **10k
⍀
SENSE 7.5pF A3 RG **10k
⍀
10k
⍀
5pF AD744 **10k
⍀
A2 REFERENCE +IN AD744
Figure 35. Upper Trace: AD744 Output Voltage for
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT
a +10 V to 0 V Step, Scale: 5 mV/div.
**RATIO MATCHED 1% METAL FILM RESISTORS
Lower Trace: Logic Input Signal, Scale: 5 V/div.
+15V +VS PIN 7
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV.
1
␮
F 1
␮
F 0.1
␮
F EACH COMM
Output settling time for the AD565/AD744 combination is less
AMPLIFIER 1
␮
F 1
␮
F 0.1
␮
F
than 500 ns to within a 2.44 mV, 1/2 LSB error band.
–15V –VS PIN 4 FOR OPTIONAL OFFSET ADJUSTMENT: TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
Figure 36. A High Performance, 3 Op Amp Instrumentation Amplifier Circuit –10– REV. D Document Outline FEATURES ac Performance dc Performance APPLICATIONS CONNECTION DIAGRAMS PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS METALIZATION PHOTOGRAPH TYPICAL CHARACTERISITICS POWER SUPPLY BYPASSING MEASURING AD744 SETTLING TIME EXTERNAL FREQUENCY COMPENSATION Using Decompensation to Extend the Gain Bandwidth Product HIGH-SPEED OP AMP APPLICATIONS TECHNIQUES DAC Buffers (I-to-V Converters) A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT Minimizing Settling Time in Real-World Applications OUTLINE DIMENSIONS ORDERING GUIDE REVISION HISTORY