Datasheet LT8610A, LT8610AB (Analog Devices) - 10

LT8610A/LT8610AB Series
PIN FUNCTIONS SYNC (Pin 1):
External Clock Synchronization Input.
BST (Pin 12):
This pin is used to provide a drive voltage, Ground this pin for low ripple Burst Mode operation at low higher than the input voltage, to the topside power switch. output loads. Tie to a clock source for synchronization to Place a 0.1µF boost capacitor as close as possible to the IC. an external frequency. Apply a DC voltage of 3V or higher
INTV
or tie to INTV
CC (Pin 13):
Internal 3.4V Regulator Bypass Pin. CC for pulse-skipping mode. When in pulse- The internal power drivers and control circuits are pow- skipping mode, the IQ will increase to several hundred µA. ered from this voltage. INTV Do not float this pin. CC maximum output cur- rent is 20mA. Do not load the INTVCC pin with external
TR/SS (Pin 2):
Output Tracking and Soft-Start Pin. This circuitry. INTVCC current will be supplied from BIAS if pin allows user control of output voltage ramp rate dur- VBIAS > 3.1V, otherwise current will be drawn from VIN. ing start-up. A TR/SS voltage below 0.97V forces the Voltage on INTVCC will vary between 2.8V and 3.4V when LT8610A/LT8610AB to regulate the FB pin to equal the VBIAS is between 3.0V and 3.6V. Decouple this pin to power TR/SS pin voltage. When TR/SS is above 0.97V, the ground with at least a 1μF low ESR ceramic capacitor tracking function is disabled and the internal reference placed close to the IC. resumes control of the error amplifier. An internal 2.2μA
BIAS (Pin 14):
The internal regulator will draw current from pull-up current from INTVCC on this pin allows a capacitor BIAS instead of V to program output voltage slew rate. This pin is pulled to IN when BIAS is tied to a voltage higher than 3.1V. For output voltages of 3.3V and above this pin ground with an internal 230Ω MOSFET during shutdown should be tied to V and fault conditions; use a series resistor if driving from OUT. If this pin is tied to a supply other than V a low impedance output. This pin may be left floating if OUT use a 1µF local bypass capacitor on this pin. the tracking function is not needed.
PG (Pin 15):
The PG pin is the open-drain output of an internal comparator. PG remains low until the FB pin is
RT (Pin 3):
A resistor is tied between RT and ground to within ±9% of the final regulation voltage, and there are set the switching frequency. no fault conditions. PG is valid when VIN is above 3.4V,
EN/UV (Pin 4):
The LT8610A/LT8610AB is shut down regardless of EN/UV pin state. when this pin is low and active when this pin is high. The
FB (Pin 16, LT8610A/LT8610AB Only):
The LT8610A/ hysteretic threshold voltage is 1.00V going up and 0.96V LT8610AB regulates the FB pin to 0.970V. Connect the going down. Tie to VIN if the shutdown feature is not feedback resistor divider tap to this pin. Also, connect a used. An external resistor divider from VIN can be used phase lead capacitor between FB and V to program a V OUT. Typically, this IN threshold below which the LT8610A/ capacitor is 4.7pF to 10pF. LT8610AB will shut down.
V V OUT (Pin 16, LT8610A-3.3/LT8610A-5/LT8610AB-3.3/ IN (Pins 5, 6):
The VIN pins supply current to the LT8610A/
LT8610AB-5 Only):
The LT8610A-3.3 and LT8610AB-3.3 LT8610AB internal circuitry and to the internal topside regulate the V power switch. These pins must be tied together and be OUT pin to 3.3V. This pin connects to a 14.3MΩ internal feedback divider that programs the fixed output. locally bypassed. Be sure to place the positive terminal of The LT8610A-5 and LT8610AB-5 regulate the V the input capacitor as close as possible to the V OUT pin IN pins, to 5V. This pin connects to a 12.5MΩ internal feedback and the negative capacitor terminal as close as possible divider that programs the fixed output. to the GND pins.
GND (Pin 8, Exposed Pad Pin 17):
Ground. These pins
NC (Pin 7):
No Connect. This pin is not connected to are the return path of the internal bottom-side switch and internal circuitry. must be tied together. Place the negative terminal of the
SW (Pins 9, 10, 11):
The SW pins are the outputs of the input capacitor as close to the GND pin and exposed pad internal power switches. Tie these pins together and con- as possible. The exposed pad must be soldered to the PCB nect them to the inductor and boost capacitor. This node in order to lower the thermal resistance. should be kept small on the PCB for good performance. Rev. B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts