Datasheet MASTERGAN2 (STMicroelectronics) - 3
| Fabricante | STMicroelectronics |
| Descripción | High power density 600V Half bridge driver with two enhancement mode GaN HEMT |
| Páginas / Página | 29 / 3 — MASTERGAN2. Pin description and connection diagram. Figure 2. Pin … |
| Formato / tamaño de archivo | PDF / 1.6 Mb |
| Idioma del documento | Inglés |
MASTERGAN2. Pin description and connection diagram. Figure 2. Pin connection (top view). 2.1. Pin list. Table 1. Pin description
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MASTERGAN2 Pin description and connection diagram 2 Pin description and connection diagram Figure 2. Pin connection (top view)
.C. N.C. N N.C. GND VCC HIN SD/OD LIN N.C. 31 30 29 28 27 26 25 24 23 GND PVCC 1 EP1 22 BOOT GL 2 21 OUTb PGND 3 20 GH SENSE 4 19 VS SENSE 5 18 VS SENSE 6 SENSE OUT 17 VS EP2 EP3 SENSE 7 16 VS SENSE 8 15 VS 9 10 11 12 13 14 OUT OUT OUT SENSE SENSE SENSE
2.1 Pin list Table 1. Pin description Pin Number Pin Name Type Function
15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain) 12, 13, 14, EP3 OUT Power Output Half-bridge output 4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source) 22 BOOT Power Supply Gate driver high-side supply voltage Gate driver high-side reference voltage, used only for Bootstrap 21 OUTb Power Supply capacitor connection. Internally connected to OUT. 27 VCC Power Supply Logic supply voltage 1 PVCC Power Supply Gate driver low-side supply voltage 28, EP1 GND Power Supply Gate driver ground Gate driver low-side buffer ground. Internally connected to 3 PGND Power Supply SENSE 26 HIN Logic Input High-Side driver logic input 24 LIN Logic Input Low-Side driver logic input 25 SD/OD Logic Input-Output Driver Shutdown input and Fault Open-Drain 2 GL Output Low-Side GaN gate 20 GH Output High-Side GaN gate 23, 29, 30, 31 N.C. Not Connected Leave floating
DS13597
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Rev 1 page 3/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures
.C. N.C. N N.C. GND VCC HIN SD/OD LIN N.C. 31 30 29 28 27 26 25 24 23 GND PVCC 1 EP1 22 BOOT GL 2 21 OUTb PGND 3 20 GH SENSE 4 19 VS SENSE 5 18 VS SENSE 6 SENSE OUT 17 VS EP2 EP3 SENSE 7 16 VS SENSE 8 15 VS 9 10 11 12 13 14 OUT OUT OUT SENSE SENSE SENSE
2.1 Pin list Table 1. Pin description Pin Number Pin Name Type Function
15, 16, 17, 18, 19 VS Power Supply High voltage supply (high-side GaN Drain) 12, 13, 14, EP3 OUT Power Output Half-bridge output 4, 5, 6, 7, 8, 9, 10, 11, EP2 SENSE Power Supply Half-bridge sense (low-side GaN Source) 22 BOOT Power Supply Gate driver high-side supply voltage Gate driver high-side reference voltage, used only for Bootstrap 21 OUTb Power Supply capacitor connection. Internally connected to OUT. 27 VCC Power Supply Logic supply voltage 1 PVCC Power Supply Gate driver low-side supply voltage 28, EP1 GND Power Supply Gate driver ground Gate driver low-side buffer ground. Internally connected to 3 PGND Power Supply SENSE 26 HIN Logic Input High-Side driver logic input 24 LIN Logic Input Low-Side driver logic input 25 SD/OD Logic Input-Output Driver Shutdown input and Fault Open-Drain 2 GL Output Low-Side GaN gate 20 GH Output High-Side GaN gate 23, 29, 30, 31 N.C. Not Connected Leave floating
DS13597
-
Rev 1 page 3/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures