Datasheet PIC32MK (Microchip) - 4

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PIC32MK GPG/MCJ with CAN FD Family Device Pin Tables TABLE 2: PIN NAMES FOR 64-PIN GENERAL PURPOSE (GPG) DEVICES 64-PIN QFN(4) AND TQFP (TOP VIEW) PIC32MK0512GPG064 PIC32MK0256GPG064
64 1 64 1
QFN(4) TQFP Pin # Full Pin Name Pin # Full Pin Name
1 TCK/RPA7/RA7 33 OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4 2 RPB14/RB14 34 AN40/CVD40/RPE0/RE0 3 RPB15/RB15 35 AN41/CVD41/RPE1/RE1 4 AN19/CVD19/RPG6/RG6 36 AN46/CVD46/RPA14/RA14 5 AN18/CVD18/RPG7/RG7 37 AN47/CVD47/RPA15/RA15 6 AN17/CVD17/RPG8/RG8 38 VDD 7 MCLR# 39 OSCI/CLKI/AN49/CVD49/RPC12/RC12 8 AN16/CVD16/RPG9/RG9 40 OSCO/CLKO/RPC15/RC15 9 VSS 41 VSS 10 VDD 42 RD8 11 AN10/CVD10/RPA12/RA12 43 PGD2/RPB5/SDA1/RB5 12 AN9/CVD9/RPA11/RA11 44 PGC2/RPB6/SCL1/RB6 13 OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0 45 DAC1/AN48/CVD48/RPC10/RC10 14 OA2IN+/AN1/C2IN1+/RPA1/RA1 46 OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7 15 PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0 47 SOSCI/RPC13
(5)
/RC13
(5)
16 PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1 48 SOSCO/RPB8(5)/T1CK(5)/RB8(5) 17 PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2 49 TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9 18 PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3 50 TRCLK/RPC6/RC6 19 AVDD 51 TRD0/RPC7/RC7 20 AVSS 52 TRD1/RPC8/RC8 21 OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0 53 TRD2/RPD5/RD5 22 OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1 54 TRD3/RPD6/RD6 23 OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/RC2 55 RPC9/RC9 24 AN11/CVD11/C1IN2-/RC11 56 VSS 25 VSS 57 VDD 26 VDD 58 RPF0/RF0 27 AN12/CVD12/C2IN2-/C5IN2-/RE12 59 RPF1/RF1 28 AN13/CVD13/C3IN2-/RE13 60 RPB10/RB10 29 AN14/CVD14/RPE14/RE14 61 RPB11/RB11 30 AN15/CVD15/RPE15/RE15 62 RPB12/RB12 31 TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8 63 RPB13/CTPLS/RB13 32 RPB4/SCL2/RB4 64 TDO/RA10
Note 1:
The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and
10.3 “Peripheral Pin Select (PPS)”
for restrictions.
2:
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
10.0 “I/O Ports”
for more information.
3:
Shaded pins are 5V tolerant.
4:
The metal heat sink pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
5:
Functions are restricted to input functions only and inputs wil be slower than the standard inputs. Change notification interrupt is not available on this pin. DS60001570C-page 4  2019-2020 Microchip Technology Inc. Document Outline TABLE 1: PIC32MK Motor Control and General Purpose (MC and GP) Family Features TABLE 2: Pin Names for 64-pin General Purpose (GPG) Devices TABLE 3: Pin Names for 64-pin Motor Control (MCJ) Devices TABLE 4: Pin Names for 48-pin General Purpose (GPG) Devices TABLE 5: Pin Names for 48-pin Motor Control (MCJ) Devices 1.0 Device Overview FIGURE 1-1: PIC32MK GPG/MCJ with CAN FD Family Block Diagram TABLE 1-1: PORTA THrough PORTG REMAPPABLE PERIPHERAL DescriptionS TABLE 1-2: POrtA through port G Pinout I/O Descriptions TABLE 1-3: Oscillator and Clock Pinout I/O Descriptions TABLE 1-4: Input Capture Pinout I/O Descriptions TABLE 1-5: Output Compare Pinout I/O Descriptions TABLE 1-6: External Interrupts Pinout I/O Descriptions TABLE 1-7: UART1 Through UART2 Pinout I/O Descriptions TABLE 1-8: SPI1 Through SPI2 Pinout I/O Descriptions TABLE 1-9: I2C1 Through I2C2 Pinout I/O Descriptions TABLE 1-10: Timer1 Through Timer9 and RTCC PInout I/O Descriptions TABLE 1-11: Comparator 1 Through Comparator 5 Pinout I/O Descriptions TABLE 1-12: Op amp 1 Through Op-Amp 5 Pinout I/O Descriptions TABLE 1-13: CAN_FD Pinout I/O Descriptions TABLE 1-14: CTMU Pinout I/O Descriptions TABLE 1-15: DAC1 and DAC2 Pinout I/O Descriptions TABLE 1-16: MCPWM1 Through MCPWM9 Pinout I/O Descriptions (Motor Control devices only) TABLE 1-17: MCPWM Fault, Current-limit, and dead time compensation Pinout I/o Descriptions (motor control devices only) TABLE 1-18: QEI1 through qei3 pinout i/o descriptions (motor control devices only) TABLE 1-19: Power, Ground, HLVD and Voltage reference pinout I/O Descriptions TABLE 1-20: JTAG, Trace, Master Clear and Programming/Debugging Pinout I/O Descriptions TABLE 1-21: Configurable Logic Cell Pinout I/O Descriptions TABLE 1-22: Capacitive Voltage Divider Pinout I/O descriptions TABLE 1-23: ADC0 - ADC5, ADC7 Pinout I/O Descriptions 2.0 Guidelines for Getting Started with 32-bit MCUs 2.1 Basic Connection Requirements 2.2 Decoupling Capacitors FIGURE 2-1: Recommended Minimum Connection 2.3 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.4 ICSP Pins 2.5 JTAG 2.6 Trace 2.7 External Oscillator Pins FIGURE 2-3: Suggested Oscillator Circuit Placement EXAMPLE 2-1: Crystal Load Capacitor Calculation FIGURE 2-4: Primary crystal oscillator circuit recommendations 2.8 Unused I/Os 2.9 Considerations When Interfacing to Remotely Powered Circuits FIGURE 2-5: PIC32 Non-5V Tolerant Circuit Example TABLE 2-1: Examples of digital/ Analog Isolators with optional level translation FIGURE 2-6: Example Digital/Analog Signal Isolation Circuits FIGURE 2-7: PIC32 5V Tolerant Pin Architecture Example 2.10 Designing for High-Speed Peripherals TABLE 2-2: Peripherals That produce HS Signals on External Pins FIGURE 2-8: Series Resistor FIGURE 2-9: EMI/EMC/EFT Suppression Circuit 2.11 Typical Application Connection Examples FIGURE 2-10: Capacitive Touch Sensing Application 2.0 CPU FIGURE 2-1: PIC32MK GPG/MCJ with CAN FD Family Microprocessor Core Block Diagram 2.1 Architecture Overview TABLE 2-1: MIPS32® microAptiv™ MCU Core High-Performance Integer Multiply/ Divide Unit Latencies and Repeat Rates TABLE 2-2: DSP-related Latencies and Repeat Rates TABLE 2-3: Coprocessor 0 Registers (Continued) TABLE 2-4: FPU Instruction Latencies and Repeat Rates TABLE 2-5: FPU (CP1) Registers 2.2 Power Management 2.3 EJTAG Debug Support 2.4 MIPS DSP ASE Extension 2.5 microMIPS ISA 2.6 MIPS32® microAptiv™ MCU Core Configuration Register 2-1: Config: Configuration Register; CP0 Register 16, Select 0 (Continued) Register 2-2: Config1: Configuration Register 1; CP0 Register 16, Select 1 Register 2-3: Config3: Configuration Register 3; CP0 Register 16, Select 3 (Continued) Register 2-4: Config4: Configuration Register 4; CP0 Register 16, Select 4 Register 2-5: Config5: Configuration Register 5; CP0 Register 16, Select 5 Register 2-6: Config7: Configuration Register 7; CP0 Register 16, Select 7 Register 2-7: FIR: Floating Point Implementation Register; CP1 Register 0 Register 2-8: FCCR: Floating Point Condition Codes Register; CP1 Register 25 Register 2-9: FEXR: Floating Point Exceptions Status Register; CP1 Register 26 Register 2-10: FENR: Floating Point Exceptions and Modes Enable Register; CP1 Register 28 Register 2-11: FCSR: Floating Point Control and Status Register; CP1 Register 31 3.0 Memory Organization 3.1 Memory Layout FIGURE 3-1: Memory Map for Devices With 256 KB Program Memory and 64 KB RAM FIGURE 3-2: Memory Map for Devices With 512 KB Program Memory and 64 KB Ram FIGURE 3-3: Boot and Alias Memory Map TABLE 3-1: SFR Memory Map TABLE 3-2: Boot Flash 1 Sequence and Configuration Words Summary 3.2 System Bus Arbitration TABLE 3-3: Initiators to Targets Access Association TABLE 3-4: Initiator ID and QOS 3.3 Permission Access and System Bus Registers TABLE 3-5: System Bus Targets and Associated Protection Registers TABLE 3-6: System Bus Register Map TABLE 3-7: System Bus Target 0 Register Map TABLE 3-8: System Bus Target 1 Register Map (Continued) TABLE 3-9: System Bus Target 2 Register Map TABLE 3-10: System Bus Target 3 Register Map Register 3-1: SBFLAG: System Bus Status Flag Register Register 3-2: SBTxELOG1: System Bus Target ‘x’ Error Log Register 1 (‘x’ = 0-3) (Continued) Register 3-3: SBTxELOG2: System Bus Target ‘x’ Error Log Register 2 (‘x’ = 0-3) Register 3-4: SBTxECON: System Bus Target ‘x’ Error Control Register (‘x’ = 0-3) Register 3-5: SBTxECLRS: System Bus Target ‘x’ Single Error Clear Register (‘x’ = 0-3) Register 3-6: SBTxECLRM: System Bus Target ‘x’ Multiple Error Clear Register (‘x’ = 0-3) Register 3-7: SBTxREGy: System Bus Target ‘x’ Region ‘y’ Register (‘x’ = 0-3; ‘y’ = 0-2) Register 3-8: SBTxRDy: System Bus Target ‘x’ Region ‘y’ Read Permissions Register (‘x’ = 0-3; ‘y’ = 0-2) Register 3-9: SBTxWRy: System Bus Target ‘x’ Region ‘y’ Write Permissions Register (‘x’ = 0-3; ‘y’ = 0-2) 4.0 Flash Program Memory 4.1 Flash Control Registers TABLE 4-1: Flash Controller Register Map Register 4-1: NVMCON: Programming Control Register (Continued) Register 4-2: NVMKEY: Programming Unlock Register Register 4-3: NVMADDR: Flash Address Register Register 4-4: NVMDATAx: Flash Data Register (x = 0-3) Register 4-5: NVMSRCADDR: Source Data Address Register Register 4-6: NVMPWP: Program Flash Write-Protect Register Register 4-7: NVMBWP: Flash Boot (Page) Write-Protect Register Register 4-8: NVMCON2: Flash Programming Control Register 2 5.0 Resets FIGURE 5-1: System Reset Block Diagram 5.1 Reset Control Registers TABLE 5-1: Resets Register Map Register 5-1: RCON: Reset Control Register Register 5-2: RSWRST: Software Reset Register Register 5-3: RNMICON: Non-Maskable Interrupt (NMI) Control Register Register 5-4: PWRCON: Power Control Register 6.0 CPU Exceptions and Interrupt Controller TABLE 6-1: ISR Latency Information FIGURE 6-1: CPU Exceptions and Interrupt Controller Module Block Diagram 6.1 CPU Exceptions Table 6-2: MIPS32® microAptiv™ MCU Core Exception Types (Continued) 6.2 Interrupts Table 6-3: Interrupt IRQ, Vector and Bit Location (Continued) 6.3 Interrupt Control Registers Table 6-4: Interrupt Register Map (Continued) Register 6-1: INTCON: Interrupt Control Register Register 6-2: PRISS: Priority Shadow Select Register (Continued) Register 6-3: INTSTAT: Interrupt Status Register Register 6-4: IPTMR: Interrupt Proximity Timer Register Register 6-5: IFSx: Interrupt Flag Status Register ‘x’ (‘x’ = 0-7) Register 6-6: IECx: Interrupt Enable Control Register ‘x’ (‘x’ = 0-7) Register 6-7: IPCx: Interrupt Priority Control Register ‘x’ (‘x’ = 0-63) (Continued) Register 6-8: OFFx: Interrupt Vector Address Offset Register (x = 0-190) 7.0 Oscillator Configuration FIGURE 7-1: PIC32MK GPG/MCJ with CAN FD Family Oscillator Diagram TABLE 7-1: System and Peripheral clock Distribution 7.1 Fail-Safe Clock Monitor (FSCM) 7.2 Oscillator Control Registers TABLE 7-2: Oscillator Configuration Register Map (Continued) Register 7-1: OSCCON: Oscillator Control Register Register 7-2: OSCTUN: FRC Tuning Register Register 7-3: SPLLCON: System PLL Control Register Register 7-4: REFOxCON: Reference Oscillator Control Register (‘x’ = 1-4) Register 7-5: REFOxTRIM: Reference Oscillator Trim Register (‘x’ = 1-4) Register 7-6: PBxDIV: Peripheral Bus ‘x’ Clock Divisor Control Register (‘x’ = 1-4, 6) Register 7-7: SLEWCON: Oscillator Slew Control Register Register 7-8: CLKSTAT: Oscillator Clock Status Register 8.0 Prefetch Module 8.1 Prefetch Cache Features FIGURE 8-1: Prefetch Module Block Diagram 8.2 Prefetch Control Registers TABLE 8-1: Prefetch Register Map Register 8-1: CHECON: Cache Module Control Register (Continued) Register 8-2: CHEHIT: CACHE Hit Status Register Register 8-3: CHEMIS: CACHE Miss Status Register 9.0 Direct Memory Access (DMA) Controller FIGURE 9-1: DMA Block Diagram 9.1 DMA Control Registers TABLE 9-1: DMA Global Register Map TABLE 9-2: DMA CRC Register Map TABLE 9-3: DMA Channel 0 THROUGH Channel 7 Register Map (Continued) Register 9-1: DMACON: DMA Controller Control Register Register 9-2: DMASTAT: DMA Status Register Register 9-3: DMAADDR: DMA Address Register Register 9-4: DCRCCON: DMA CRC Control Register (Continued) Register 9-5: DCRCDATA: DMA CRC Data Register Register 9-6: DCRCXOR: DMA CRCXOR Enable Register Register 9-7: DCHxCON: DMA Channel ‘x’ Control Register (‘x’ = 0-7) (Continued) Register 9-8: DCHxECON: DMA Channel x Event Control Register Register 9-9: DCHxINT: DMA Channel x Interrupt Control Register (Continued) Register 9-10: DCHxSSA: DMA Channel x Source Start Address Register Register 9-11: DCHxDSA: DMA Channel x Destination Start Address Register Register 9-12: DCHxSSIZ: DMA Channel x Source Size Register Register 9-13: DCHxDSIZ: DMA Channel x Destination Size Register Register 9-14: DCHxSPTR: DMA Channel x Source Pointer Register Register 9-15: DCHxDPTR: DMA Channel x Destination Pointer Register Register 9-16: DCHxCSIZ: DMA Channel x Cell-Size Register Register 9-17: DCHxCPTR: DMA Channel x Cell Pointer Register Register 9-18: DCHxDAT: DMA Channel x Pattern Data Register 10.0 I/O Ports FIGURE 10-1: Block Diagram of a Typical Multiplexed Port Structure 10.1 Parallel I/O (PIO) Ports 10.2 CLR, SET, and INV Registers 10.3 Peripheral Pin Select (PPS) FIGURE 10-2: Remappable Input Example for U1RX TABLE 10-1: Input Pin Selection (Continued) FIGURE 10-3: Example of Multiplexing of Remappable Output for RPF0 TABLE 10-2: Output Pin Selection (Continued) 10.4 I/O Ports Control Registers TABLE 10-3: PORTA Register Map TABLE 10-4: PORTB Register Map TABLE 10-5: PORTC Register Map TABLE 10-6: PORTD Register Map TABLE 10-7: PORTE Register Map TABLE 10-8: PORTf Register Map TABLE 10-9: PORTG Register Map TABLE 10-10: Peripheral Pin Select Input Register Map (Continued) TABLE 10-11: Peripheral Pin Select Output Register Map (Continued) Register 10-1: [pin name]R: Peripheral Pin Select Input Register Register 10-2: RPnR: Peripheral Pin Select Output Register Register 10-3: CNCONx: Change Notice control for PORTx Register (x = A – G) 11.0 Timer1 11.1 Additional Supported Features 11.2 TImer1 Usage Model Guidelines FIGURE 11-1: Timer1 Block Diagram 11.3 Timer1 Control Register TABLE 11-1: Timer1 Register Map Register 11-1: T1CON: Type A Timer Control Register (Continued) 12.0 Timer2 Through Timer9 12.1 Features 12.2 Timer2-Timer9 Formula FIGURE 12-1: Timer2 through Timer9 Block Diagram (16/32-bit) FIGURE 12-2: Timer Synchronization Block Diagram 12.3 Timer2-Timer9 Control Registers TABLE 12-1: Timer2 THROUGH Timer9 Register Map (Continued) Register 12-1: TxCON: Type B Timer Control Register (‘x’ = 2-9) 13.0 Deadman Timer (DMT) FIGURE 13-1: Deadman Timer Block diagram 13.1 Deadman Timer Control Registers TABLE 13-1: Deadman Timer Register Map Register 13-1: DMTCON: Deadman Timer Control Register Register 13-2: DMTPRECLR: Deadman Timer Preclear Register Register 13-3: DMTCLR: Deadman Timer Clear Register Register 13-4: DMTSTAT: Deadman Timer Status Register Register 13-5: DMTCNT: Deadman Timer Count Register Register 13-6: DMTPSCNT: Post Status Configure DMT Count Status Register Register 13-7: DMTPSINTV: Post Status Configure DMT Interval Status Register 14.0 Watchdog Timer (WDT) Figure 14-1: Watchdog Timer Block Diagram 14.1 Watchdog Timer Control Registers TABLE 14-1: Watchdog Timer Register Map Register 14-1: WDTCON: Watchdog Timer Control Register 15.0 Input Capture FIGURE 15-1: Input Capture Block Diagram TABLE 15-1: Timer Source Configurations 15.1 Input Capture Control Registers TABLE 15-2: Input Capture 1 THROUGH Input Capture 9 Register Map Register 15-1: ICxCON: Input Capture ‘x’ Control Register (‘x’ = 1-9) (Continued) 16.0 Output Compare FIGURE 16-1: Output Compare Module Block Diagram TABLE 16-1: Timer Source Configurations 16.1 Output Compare Control Registers Register 16-1: OCxCON: Output Compare ‘x’ Control Register (‘x’ = 1-16) 17.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) FIGURE 17-1: SPI/I2S Module Block Diagram 17.1 SPI Control Registers TABLE 17-1: spi1 and SPI2 Register Map Register 17-1: SPIx CON: SPI Control Register (Continued)(x=1-2) Register 17-2: SPIxCON2: SPI Control Register 2 (x=1-2) Register 17-3: SPIxSTAT: SPI Status Register (x=1-2) Register 17-4: SPIxBUF: SPIx Buffer Register (x = 1-2) Register 17-5: SPIxBRG: SPIx Baud Rate Generator Register (x= 1-2) 18.0 Inter-Integrated Circuit (I2C) FIGURE 18-1: I2C Block Diagram 18.1 I2C Control Registers TABLE 18-1: I2C1 and I2C2 Register Map Register 18-1: I2CxCON: I2C Control Register (Continued) (x=1-2) Register 18-2: I2CxSTAT: I2C Status Register (Continued)(x=1-2) Register 18-3: I2CxBRG: – I2C MODULE BAUDRATE REGISTER (x=1-2) EQUATION 18-1: Baud Rate Generator Reload Value Calculation EQUATION 18-2: SCK Frequency 19.0 Universal Asynchronous Receiver Transmitter (UART) FIGURE 19-1: UART Simplified Block Diagram 19.1 UART Control Registers TABLE 19-1: UART1 and UART2 Register Map Register 19-1: UxMODE: UARTx Mode Register (Continued)(“x” = 1-2) Register 19-2: UxSTA: UARTx Status and Control Register (Continued)(“x” = 1-2) Register 19-3: UxRXREG: UARTx Receive Register (“x” = 1-2) Register 19-4: UxTXREG: UARTx Transmit Register (“x” = 1-2) Register 19-5: UxBRG: UARTx Baud Rate Generator Register (“x” = 1-2) TABLE 19-2: UART Baud Rate Calculations 19.2 UART Broadcast Mode Example TABLE 19-3: PDSEL<1:0> (Uxmode<2:1>) = ‘0b11 and ADM_EN (UxSTA<24>) = 1 19.3 Module Operation 19.4 Serial Protocols Usage 19.5 Transmit and Receive Timing FIGURE 19-2: UART Reception FIGURE 19-3: Transmission (8-bit or 9-bit Data) 20.0 Configurable Logic Cell (CLC) FIGURE 20-1: CLCx Module FIGURE 20-2: CLCx Logic Function Combinatorial Options FIGURE 20-3: CLCx Input Source Selection Diagram 20.1 Control Registers TABLE 20-1: CLC1, CLC2 and CLC3 Register Map Register 20-1: CLCxCON: CLCx Control Register (Continued) Register 20-2: CLCxSEL: CLCx Input MUX Select Register (Continued) Register 20-3: CLCxGLS: CLCx Gate Logic Input Select Register (Continued) 22.0 Real-Time Clock and Calendar (RTCC) FIGURE 22-1: RTCC Block Diagram 22.1 RTCC Control Registers TABLE 22-1: RTCC Register Map Register 22-1: RTCCON: Real-Time Clock and Calendar Control Register (Continued) Register 22-2: RTCALRM: Real-Time Clock ALARM Control Register (Continued) Register 22-3: RTCTIME: Real-Time Clock Time Value Register Register 22-4: RTCDATE: Real-Time Clock Date Value Register Register 22-5: ALRMTIME: Alarm Time Value Register Register 22-6: ALRMDATE: Alarm Date Value Register 23.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to- Digital Converter (ADC) 23.1 Activation Sequence TABLE 23-1: PIC32MKxxx based on 60 MHz Tad clock (16.667 ns) FIGURE 23-1: ADC Block Diagram FIGURE 23-2: S&H Block Diagram 23.2 ADC Control Registers TABLE 23-2: ADC Register Map (Continued) Register 23-1: ADCCON1: ADC Control Register 1 (Continued) Register 23-2: ADCCON2: ADC Control Register 2 (Continued) Register 23-3: ADCCON3: ADC Control Register 3 (Continued) Register 23-4: ADCTRGMODE: ADC Triggering Mode for Dedicated ADC Register (Continued) Register 23-5: ADCIMCON1: ADC Input Mode Control Register 1 (Continued) Register 23-6: ADCIMCON2: ADC Input Mode Control Register 2 (Continued) Register 23-7: ADCIMCON3: ADC Input Mode Control Register 3 (Continued) Register 23-8: ADCIMCON4: ADC Input Mode Control Register 4 Register 23-9: ADCGIRQEN1: ADC Global Interrupt Enable Register 1 Register 23-10: ADCGIRQEN2: ADC Global Interrupt Enable Register 2 Register 23-11: ADCCSS1: ADC Common Scan Select Register 1 Register 23-12: ADCCSS2: ADC Common Scan Select Register 2 Register 23-13: ADCDSTAT1: ADC Data Ready Status Register 1 Register 23-14: ADCDSTAT2: ADC Data Ready Status Register 2 Register 23-15: ADCCMPENx: ADC Digital Comparator ‘x’ Enable Register (‘x’ = 1 through 4) Register 23-16: ADCCMPx: ADC Digital Comparator ‘x’ Limit Value Register (‘x’ = 1 through 4) Register 23-17: ADCFLTRx: ADC Digital Filter ‘x’ Register (‘x’ = 1 through 6) (Continued) Register 23-18: ADCTRG1: ADC Trigger Source 1 Register Register 23-19: ADCTRG2: ADC Trigger Source 2 Register Register 23-20: ADCTRG3: ADC Trigger Source 3 Register Register 23-21: ADCTRG4: ADC Trigger Source 4 Register Register 23-22: ADCTRG5: ADC Trigger Source 5 Register Register 23-23: ADCTRG6: ADC Trigger Source 6 Register Register 23-24: ADCTRG7: ADC Trigger Source 7 Register Register 23-25: ADCCMPCON1: ADC Digital Comparator 1 Control Register (Continued) Register 23-26: ADCCMPCONx: ADC Digital Comparator ‘x’ Control Register (‘x’ = 2 through 4) (Continued) Register 23-27: ADCBASE: ADC Base Register Register 23-28: ADCDSTAT: ADC DMA Status Register (Continued) Register 23-29: ADCCNTB: ADC Channel Sample Count Base Address Register Register 23-30: ADCDMAB: ADC Channel Sample Count Base Address Register Register 23-31: ADCDATAx: ADC Output Data Register (‘x’ = 0-27, 33-41, and 45-53) Register 23-32: ADCTRGSNS: ADC Trigger Level/Edge Sensitivity Register Register 23-33: ADCxTIME: Dedicated High-Speed ADCx Timing Register (Continued) (‘x’ = 0 through 5) Register 23-34: ADCEIEN1: ADC Early Interrupt Enable Register 1 Register 23-35: ADCEIEN2: ADC Early Interrupt Enable Register 2 Register 23-36: ADCEISTAT1: ADC Early Interrupt Status Register 1 Register 23-37: ADCEISTAT2: ADC Early Interrupt Status Register 2 Register 23-38: ADCANCON: ADC Analog Warm-up Control Register (Continued) Register 23-39: ADCxCFG: ADCx Configuration Register (‘x’ = 0 through 5 and 7) Register 23-40: ADCSYSCFG0: ADC System Configuration Register 0 Register 23-41: ADCSYSCFG1: ADC System Configuration Register 1 24.1 Control Registers TABLE 24-1: CAN FD Peripheral Register Summary (Continued) 24.0 Controller Area Network with Flexible Data-rate (CAN FD) FIGURE 24-1: PIC32MK CAN FD Module Block Diagram 24.2 Control Registers Register 24-1: CFd1con: CAN Control Register(2) Register 24-2: CFd1nbtcfg: Nominal Bit Time Configuration Register (4) Register 24-3: CFd1dBTCFG: Data Bit Time Configuration Register (Continued)(4) Register 24-4: CFD1TDC: Transmitter Delay Compensation Register (1,2) Register 24-5: CFD1TBC: CAN Time Base Counter Register(1,2) Register 24-6: CFD1TSCON: CAN Time Stamp Control Register (1) Register 24-7: CFD1VEC: Interrupt Code Register (1,2) Register 24-8: CFD1INT: Interrupt Register (1,2) Register 24-9: CFD1RXIF: Receive Interrupt Status Register (2) Register 24-10: CFD1RXOVIF: Receive Overflow Interrupt Status Register (2) Register 24-11: CFD1TXIF: Transmit Interrupt Status Register (3) Register 24-12: CFD1TXATIF: Transmit Attempt Interrupt Status Register (3) Register 24-13: CFD1TXREQ: Transmit Request Register (2) Register 24-14: CFD1FIFOBA: Message Memory Base Address Register(1,2,3) Register 24-15: CFD1TXQCON: Transmit Queue Control Register(3) Register 24-16: CFD1TXQSTA: Transmit Queue Status Register (4) Register 24-17: CFD1FIFOCONn: FIFO Control Register (‘n’ = 1-31) (4) (Continued) Register 24-18: CFD1TXQSTAn: Transmit Queue Status Register (‘n’ = 1-31) (4) (Continued) Register 24-19: CFD1TEFCON: Transmit Event FIFO Control Register(2) Register 24-20: CFD1TEFSTA: Transmit Event FIFO Status Register Register 24-21: CFD1FIFOUAn: Definition Register (‘n’ = 1-31) Register 24-22: CFD1TEFUA: Transmit Event FIFO User Address Register Register 24-23: CFD1TXQUA: Transmit Queue User Address Register Register 24-24: CFD1TREC: Transmit/Receive Error Count Register Register 24-25: CFD1BDIAG0: Bus Diagnostics Register 0 Register 24-26: CFD1BDIAG1: Bus Diagnostics Register 1 (Continued) Register 24-27: CFD1FLTCON0: Filter Control Register (Continued) Register 24-28: CFD1FLTCON1: Filter Control Register (Continued) Register 24-29: CFD1FLTCON2: Filter Control Register (Continued) Register 24-30: CFD1FLTCON3: Filter Control Register (Continued) Register 24-31: CFD1FLTCON4: Filter Control Register (Continued) Register 24-32: CFD1FLTCON5: Filter Control Register (Continued) Register 24-33: CFD1FLTCON6: Filter Control Register (Continued) Register 24-34: CFD1FLTCON7: Filter Control Register (Continued) Register 24-35: CFD1FLTOBJn: Filter Object Register (‘n’ = 0-31) Register 24-36: CFD1MASKn: Mask Register (‘n’ = 0-31) 25.0 Op Amp/Comparator Module FIGURE 25-1: Op amp 1/Comparator 1 Module Block Diagram FIGURE 25-2: Op amp 2/Comparator 2 Module Block Diagram FIGURE 25-3: Op amp 3/Comparator 3 Module Block Diagram FIGURE 25-4: Comparator 4 Module Block Diagram FIGURE 25-5: Op amp 5/Comparator 5 Module Block Diagram 25.1 Comparator Interface 25.2 Comparator Output Blanking FIGURE 25-6: User Programmable Blanking Function Diagram 25.3 Comparator Output Filtering FIGURE 25-7: Digital Filter Interconnect Block Diagram 25.4 Op amp Interface TABLE 25-1: Op amp(x) functional modes (x=1-3, 5) 25.5 Op amp Mode 25.6 Op amp Unity Gain Mode 25.7 Op-Amp High performance MODE 10Mhz-100Mhz USE REQUIREMENTS (CMxCON<OPLPWR> = 0) FIGURE 25-8: OP-AMP UNITY GAIN HIGH PERFORMANCE ≥ 10 MHz SINGLE ENDED MODE REQUIREMENTS (CMxCON<OPLPWR> = 0) FIGURE 25-9: OP-AMP GAIN ≥ 2: HIGH PERFORMANCE ≥ 10 MHz SINGLE ENDED MODE REQUIREMENTS (CMxCON<OPLPWR> = 0) FIGURE 25-10: OP-AMP HIGH PERFORMANCE ≥ 10 MHz DIFFERENTIAL MODE REQUIREMENTS (CMxCON<OPLPWR> = 0) FIGURE 25-11: OP-AMP UNITY GAIN LOW POWER MODE ≤10MHZ REQUIREMENTS (CMxCON<OPLPWR> = 1) FIGURE 25-12: OP-AMP GAIN ≥ 2: LOW POWER MODE ≤10MHZ REQUIREMENTS (CMxCON<OPLPWR> = 1) FIGURE 25-13: OP AMP LOW POWER DIFFERENTIAL MODE ≤10MHZ REQUIREMENTS (CMxCON<OPLPWR> = 1) 25.8 Op-amp Circuit Examples FIGURE 25-14: Op amp Configuration circuit examples FIGURE 25-15: OP AMP Configuration Circuit ExAMples FIGURE 25-16: Op amp Configuration circuit examples FIGURE 25-17: Op amp Configuration circuit examples FIGURE 25-18: Op amp Configuration circuit examples 25.9 Comparator Configuration FIGURE 25-19: Comparator Configuration for Default Built-in Hysteresis TABLE 25-2: comparator CMPx Output and event polarity selection (x=1-5) 25.10 Op amp/Comparator Control Registers TABLE 25-3: Op amp/Comparator Register Map Register 25-1: CMSTAT: Op amp/Comparator Status Register Register 25-2: CMxCON: Op amp/Comparator ‘x’ Control Register (‘x’ = 1-5) (Continued) Register 25-3: CMxMSKCON: Comparator ‘x’ Mask Control Register (‘x’ = 1-5) (Continued) 26.0 Charge Time Measurement Unit (CTMU) FIGURE 26-1: CTMU Block Diagram 26.1 Control Registers TABLE 26-1: CTMU Register Map Register 26-1: CTMUCON: CTMU Control Register (Continued) 27.0 Control Digital-to- Analog Converter (CDAC) FIGURE 27-1: CDAC Block Diagram Register 27-1: DACxCON: CDAC Control Register ‘x’ (‘x’ = 2 through 3) TABLE 27-1: CDAC Register Map 28.0 Quadrature Encoder Interface (QEI) FIGURE 28-1: QEI Block Diagram 28.1 QEI Control Registers TABLE 28-1: QEI1 through QEI6 Register Map (Continued) Register 28-1: QEIxCON: QEIx Control Register (‘x’ = 1-3) (Continued) Register 28-2: QEIxIOC: QEIx I/O Control Register (‘x’ = 1-3) (Continued) Register 28-3: QEIxSTAT: QEIx Status Register (‘x’ = 1-3) (Continued) Register 28-4: POSxCNT: Position Counter Register (‘x’ = 1-3) Register 28-5: VELxCNT: Velocity Counter Register (‘x’ = 1-3) Register 28-6: VELxHLD: Velocity Hold Register (‘x’ = 1-3) Register 28-7: INTxHLD: Interval Timer Hold Register (‘x’ = 1-3) Register 28-8: INDxCNT: Index Counter Register (‘x’ = 1-3) Register 28-9: INTxTMR: Interval Timer Register (‘x’ = 1-3) Register 28-10: QEIxICC: QEIx Initialize/Capture/Compare Register (‘x’ = 1-3) Register 28-11: QEIxCMPL: Capture Low Register (‘x’ = 1-3) 29.0 Motor Control PWM Module FIGURE 29-1: Motor Control PWM Module Architectural Overview FIGURE 29-2: 3 Phase AC Motor Control Example 29.1 PWM Faults EXAMPLE 29-1: PWM Write-Protected Register Unlock Sequence FIGURE 29-3: Motor Control PWM Module Register Interconnection Diagram 29.2 Motor Control PWM Control Registers TABLE 29-1: MCPWM Register Map (Continued) Register 29-1: PTCON: PWM Primary Time Base Control Register (Continued) Register 29-2: PTPER: Primary Master Time Base Period Register Register 29-3: SEVTCMP: PWM Primary Special Event Compare Register Register 29-4: PMTMR: Primary Master Time Base Timer Register Register 29-5: STCON: Secondary Master Time Base Control Register Register 29-6: STPER: Secondary Master Time Base Period Register Register 29-7: SSEVTCMP: PWM Secondary Special Event Compare Register Register 29-8: SMTMR: Secondary Master Time Base Timer Register Register 29-9: CHOP: PWM Chop Clock Generator Register Register 29-10: PWMKEY: PWM Unlock Register Register 29-11: PWMCONx: PWM Control Register ‘x’ (‘x’ = 1 through 12) (Continued) Register 29-12: IOCONx: PWMx I/O Control Register ‘x’ (‘x’ = 1 through 9) (Continued) Register 29-13: PDCx: PWM Generator Duty Cycle Register ‘x’ (‘x’ = 1 through 12) Register 29-14: SDCx: PWM Secondary Duty Cycle Register ‘x’ (‘x’ = 1 through 12) Register 29-15: PHASEx: PWM Primary Phase Shift Register ‘x’ (‘x’ = 1 through 12) Register 29-16: DTRx: PWM Dead Time Register ‘x’ (‘x’ = 1 through 12) Register 29-17: ALTDTRx: PWM Alternate Dead Time Register ‘x’ (‘x’ = 1 through 12) Register 29-18: DTCOMPx: Dead Time Compensation Register ‘x’ (‘x’ = 1 through 12) Register 29-19: TRIGx: PWM Primary Trigger Compare Value Register ‘x’ (‘x’ = 1 through 12) Register 29-20: TRGCONx: PWM Trigger Control Register ‘x’ (‘x’ = 1 through 12) (Continued) Register 29-21: STRIGx: Secondary PWM Trigger Compare Register ‘x’ (‘x’ = 1 through 12) Register 29-22: CAPx: PWM Timer Capture Register ‘x’ (‘x’ = 1 through 12) Register 29-23: LEBCONx: Leading-Edge Blanking Control Register ‘x’ (‘x’ = 1 through 12) Register 29-24: LEBDLYx: Leading-Edge Blanking Delay Register ‘x’ (‘x’ = 1 through 12) Register 29-25: AUXCONx: PWM Auxiliary Control Register ‘x’ (‘x’ = 1 through 9) Register 29-26: PTMRx: PWM Timer Register ‘x’ (‘x’ = 1 through 12) 30.0 High/Low-Voltage Detect (HLVD) FIGURE 30-1: Programmable HLVD Module Block Diagram 30.1 Control Registers TABLE 30-1: HLVD Register Map Register 30-1: HLVDCON: High/Low-Voltage Detect Control Register 31.0 Power-Saving Features 31.1 Power Saving with CPU Running 31.2 Power-Saving with CPU Halted FIGURE 31-1: Low-Power Device Block Diagram 31.3 Peripheral Module Disable TABLE 31-1: Peripheral Module Disable Register Summary TABLE 31-2: Peripheral Module Disable Bits and Locations (Continued) 32.0 Special Features 32.1 Configuration Bits 32.2 Registers TABLE 32-1: DEVCFG: Device Configuration Word Summary TABLE 32-2: ADEVCFG: Alternate Device Configuration Word Summary TABLE 32-3: Device ID, Revision, and Configuration Summary TABLE 32-4: Device ADC Calibration Summary TABLE 32-5: Device EE Data Calibration Summary TABLE 32-6: Device Serial Number Summary Register 32-1: DEVSIGN0: Device Signature Word 0 Register Register 32-2: DEVCP0: Device Code-Protect 0 Register Register 32-3: DEVCFG0/ADEVCFG0: Device/Alternate Device Configuration Word 0 (Continued) Register 32-4: DEVCFG1/ADEVCFG1: Device/Alternate Device Configuration Word 1 (Continued) Register 32-5: DEVCFG2/ADEVCFG2: Device/Alternate Device Configuration Word 2 (Continued) Register 32-6: DEVCFG3/ADEVCFG3: Device/Alternate Device Configuration Word 3 Register 32-7: CFGCON: Configuration Control Register (Continued) Register 32-8: CFGPG: Permission Group Configuration Register Register 32-9: DEVID: Device and Revision ID Register Register 32-10: DEVADCx: Device ADC Calibration Register ‘x’ (‘x’ = 0-5, 7) Register 32-11: DEVSNx: Device Serial Number Register ‘x’ (‘x’ = 0-3) 32.3 On-Chip Voltage Regulator 32.4 On-chip Temperature Sensor 32.5 Programming and Diagnostics FIGURE 32-1: Block Diagram of Programming, Debugging and Trace Ports 33.0 Instruction Set 34.0 Migration Guide TABLE 34-1: PIC32mkxxgpd/gpexx to pic32mkxxgpgxx Migration REference TABLE 34-2: 64 pin pic32mkxxgpd/e to pic32mkxxgpg function migration mismatches (Continued) 35.0 Development Support 35.1 MPLAB X Integrated Development Environment Software 35.2 MPLAB XC Compilers 35.3 MPASM Assembler 35.4 MPLINK Object Linker/ MPLIB Object Librarian 35.5 MPLAB Assembler, Linker and Librarian for Various Device Families 35.6 MPLAB X SIM Software Simulator 35.7 MPLAB REAL ICE In-Circuit Emulator System 35.8 MPLAB ICD 3 In-Circuit Debugger System 35.9 PICkit 3 In-Circuit Debugger/ Programmer 35.10 MPLAB PM3 Device Programmer 35.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 35.12 Third-Party Development Tools 36.0 Electrical Characteristics 36.1 DC Characteristics TABLE 36-1: Operating MIPS Versus Voltage TABLE 36-2: Thermal Operating Conditions TABLE 36-3: Thermal Packaging Characteristics TABLE 36-4: DC Temperature and Voltage Specifications TABLE 36-5: Electrical Characteristics: BOR TABLE 36-6: DC Characteristics: Operating Current (IDD Run Current with Peripheral Clocks Enabled)(1,2) TABLE 36-7: DC Characteristics: Idle Current (Iidle) TABLE 36-8: DC Characteristics: Power-Down Current (Ipd) TABLE 36-9: DC Characteristics: I/O Pin Input Specifications TABLE 36-10: DC Characteristics: I/O Pin Input Injection current Specifications TABLE 36-11: DC Characteristics: I/O Pin Output Specifications (Continued) TABLE 36-12: DC Characteristics: Program Memory(3) TABLE 36-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES FOR ACTIVE HIGH POWER MODE (Continued) 36.2 AC Characteristics and Timing Parameters FIGURE 36-1: Load Conditions for Device Timing Specifications TABLE 36-14: Capacitive Loading Requirements on Output Pins FIGURE 36-2: External Clock Timing TABLE 36-15: External Clock Timing Requirements TABLE 36-16: System PLL Timing Requirements TABLE 36-17: Internal FRC Accuracy TABLE 36-18: Internal LPRC Accuracy TABLE 36-19: Internal BFRC Accuracy TABLE 36-20: Comparator Specifications FIGURE 36-3: I/O Timing Characteristics TABLE 36-21: I/O Timing Requirements (Continued) FIGURE 36-4: Power-On Reset Timing Characteristics FIGURE 36-5: External Reset Timing Characteristics TABLE 36-22: Resets Timing FIGURE 36-6: Timer1-Timer9 External Clock Timing Characteristics TABLE 36-23: Timer1 External Clock Timing Requirements(1) TABLE 36-24: Timer2-Timer9 External Clock Timing Requirements FIGURE 36-7: Input Capture (CAPx) Timing Characteristics TABLE 36-25: Input Capture Module Timing Requirements FIGURE 36-8: Output Compare Module (OCx) Timing Characteristics TABLE 36-26: Output Compare Module Timing Requirements FIGURE 36-9: OCx/PWM Module Timing Characteristics TABLE 36-27: Simple OCx/PWM Mode Timing Requirements TABLE 36-28: Op Amp Specifications TABLE 36-29: Unity Gain Op amp Timing Requirements FIGURE 36-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics TABLE 36-30: SPIx Master Mode (CKE = 0, SMP = 1) Timing Requirements (Continued) FIGURE 36-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics TABLE 36-31: SPIx Module Master Mode (CKE = 1, SMP = 1) Timing Requirements (Continued) FIGURE 36-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics TABLE 36-32: SPIx Module Slave Mode (CKE = 0, SMP = 1) Timing Requirements (Continued) FIGURE 36-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics TABLE 36-33: SPIx Module Slave Mode (CKE = 1, SMP = 1) Timing Requirements (Continued) Figure 36-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode) Figure 36-15: I2Cx Bus Data Timing Characteristics (Master Mode) TABLE 36-34: I2Cx Bus Data Timing Requirements (Master Mode) (Continued) Figure 36-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode) Figure 36-17: I2Cx Bus Data Timing Characteristics (Slave Mode) TABLE 36-35: I2Cx Bus Data Timing Requirements (Slave Mode) (Continued) FIGURE 36-18: QEI Module External Clock Timing Characteristics TABLE 36-36: QEI module External Clock Timing Requirements FIGURE 36-19: QEA/QEB Input Characteristics TABLE 36-37: Quadrature Decoder Timing Requirements FIGURE 36-20: CANFDx Module I/O Timing Characteristics TABLE 36-38: CANFDx Module I/O Timing Requirements TABLE 36-39: ADC Module Specifications TABLE 36-40: Analog-to-Digital Conversion Timing Requirements TABLE 36-41: ADC Sample Times with CVD Enabled TABLE 36-42: Control DAC (CDAC) Specifications TABLE 36-43: CTMU Current Source Specifications TABLE 36-44: UART Timing Characteristics FIGURE 36-21: Motor Control PWM Module fault Timing Characteristics TABLE 36-45: Motor Control PWM Module Timing Requirements FIGURE 36-22: Low Voltage Detect Characteristics Table 36-46: Electrical Characteristics LVD FIGURE 36-23: EJTAG Timing Characteristics TABLE 36-47: EJTAG Timing Requirements 37.0 AC and DC Characteristics Graphs FIGURE 37-1: Voh – 4x Driver Pins FIGURE 37-2: Vol – 4x Driver Pins FIGURE 37-3: Voh – 8x Driver Pins FIGURE 37-4: Vol – 8x Driver Pins 38.0 Packaging Information 38.1 Package Marking Information 38.2 Package Details Appendix A: Revision History INDEX AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE