Datasheet PIC18F26/46/56Q84 (Microchip)
| Fabricante | Microchip |
| Descripción | 28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology |
| Páginas / Página | 1144 / 1 — PIC18F26/46/56Q84. 28/40/44/48-Pin, Low-Power, High-Performance. … |
| Formato / tamaño de archivo | PDF / 17.2 Mb |
| Idioma del documento | Inglés |
PIC18F26/46/56Q84. 28/40/44/48-Pin, Low-Power, High-Performance. Microcontroller with XLP Technology. Introduction
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PIC18F26/46/56Q84 28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology Introduction
The PIC18-Q84 microcontroller family is available in 28/40/44/48-pin devices for many automotive and industrial applications. The many communication peripherals found on the product family, such as CAN, SPI, I2C, two UARTs, can handle a wide range of wired and wireless (using external modules) communication protocols for intelligent applications. Combined with the Core Independent Peripherals integration capabilities, this capacity enables functions for motor control, power supply, sensor, signal and user interface applications. Additionally, this family includes a 12-bit ADC with Computation and Context Switching extensions for automated signal analysis to reduce the complexity of the application.
PIC18-Q84 Family Types Table 1. Devices Included in This Data Sheet T/ imer imer imer aveform imers 2 C oltage Detect atchdog T Device CCP (bytes) (bytes) (bytes) I/O Pins/ imer with HL CAN FD SPI/I UART/ Data SRAM Generator Oscillator 8-Bit DAC Data EEPROM 16-Bit T Comparator/ 16-Bit Dual PWM/ Zero-Cross Detect ectored Interrupts AG Boundary Scan Peripheral Pin Select 8-Bit T V Program Memory Flash 16-Bit Universal T Numerically Controlled Temperature Indicator JT Memory Access Partition/ Device Information Area Configurable Logic Cell indowed W Complimentary W Signal Measurement T High-Low V 32-Bit CRC with Scanner UART with Protocol Support Peripheral Module Disable Direct Memory Access (DMA) W 12-Bit ADC w/Computation and Context Switching (channels)
PIC18F26Q84 128k 12800 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y PIC18F46Q84 128k 12800 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y PIC18F56Q84 128k 12800 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 43 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y
Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input – 62.5 ns minimum instruction cycle • Eight Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces © 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002259A-page 1 Document Outline Introduction PIC18-Q84 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables 4. Guidelines for Getting Started with PIC18-Q84 Microcontrollers 4.1. Basic Connection Requirements 4.2. Power Supply Pins 4.2.1. Decoupling Capacitors 4.2.2. Tank Capacitors 4.3. Master Clear (MCLR) Pin 4.4. In-Circuit Serial Programming™ (ICSP™) Pins 4.5. External Oscillator Pins 4.6. Unused I/Os 5. Register and Bit Naming Conventions 5.1. Register Names 5.2. Bit Names 5.2.1. Short Bit Names 5.2.2. Long Bit Names 5.2.3. Bit Fields 5.3. Register and Bit Naming Exceptions 5.3.1. Status, Interrupt, and Mirror Bits 6. Register Legend 7. PIC18 CPU 7.1. System Arbitration 7.1.1. Priority Lock 7.2. Memory Access Scheme 7.2.1. ISR Priority > Main Priority > Peripheral Priority 7.2.2. Peripheral Priority > ISR Priority > Main Priority 7.2.3. ISR Priority > Peripheral Priority > Main Priority 7.2.4. Peripheral 1 Priority > ISR Priority > Main Priority > Peripheral 2 Priority 7.3. 8x8 Hardware Multiplier 7.3.1. Operation 7.3.2. 16x16 Unsigned Multiplication Algorithm 7.3.3. 16x16 Signed Multiplication Algorithm 7.4. PIC18 Instruction Cycle 7.4.1. Instruction Flow/Pipelining 7.4.2. Instructions in Program Memory 7.4.3. Multi-Word Instructions 7.5. STATUS Register 7.6. Call Shadow Register 7.7. Register Definitions: System Arbiter 7.7.1. ISRPR 7.7.2. MAINPR 7.7.3. DMAxPR 7.7.4. SCANPR 7.7.5. PRLOCK 7.7.6. PROD 7.7.7. STATUS 7.8. Register Summary - System Arbiter Control 8. Device Configuration 8.1. Configuration Settings 8.2. Code Protection 8.3. User ID 8.4. Device ID and Revision ID 8.5. Register Definitions: Configuration Words 8.5.1. CONFIG1 8.5.2. CONFIG2 8.5.3. CONFIG3 8.5.4. CONFIG4 8.5.5. CONFIG5 8.5.6. CONFIG6 8.5.7. CONFIG7 8.5.8. CONFIG8 8.5.9. CONFIG9 8.5.10. CONFIG10 8.5.11. CONFIG11 8.5.12. CRC Boot Polynomial 8.5.13. CRC Boot Seed 8.5.14. CRC Boot Expected Value 8.5.15. CRC Polynomial 8.5.16. CRC Seed 8.5.17. CRC Expected Value 8.6. Register Summary - Configuration Settings 8.7. Register Definitions: Device ID and Revision ID 8.7.1. Device ID 8.7.2. Revision ID 8.8. Register Summary - DEVID/REVID 9. Memory Organization 9.1. Program Memory Organization 9.1.1. Memory Access Partition 9.1.1.1. Application Block 9.1.1.2. Boot Block 9.1.1.3. Storage Area Flash 9.1.2. Program Counter 9.1.3. Return Address Stack 9.1.3.1. Top-of-Stack Access 9.1.3.2. Return Stack Pointer 9.1.3.3. PUSH and POP Instructions 9.1.3.4. Fast Register Stack 9.1.4. Look-up Tables in Program Memory 9.1.4.1. Computed GOTO 9.1.4.2. Program Flash Memory Access 9.2. Device Information Area 9.2.1. Microchip Unique Identifier (MUI) 9.2.2. External Unique Identifier (EUI) 9.2.3. Standard Parameters for the Temperature Sensor 9.2.4. Fixed Voltage Reference Data 9.3. Device Configuration Information 9.4. Data Memory Organization 9.4.1. Bank Select Register 9.4.2. Access Bank 9.5. Data Addressing Modes 9.5.1. Inherent and Literal Addressing 9.5.2. Direct Addressing 9.5.3. Indirect Addressing 9.5.3.1. FSR Registers and the INDF Operand 9.5.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 9.5.3.3. Operations by FSRs on FSRs 9.6. Data Memory and the Extended Instruction Set 9.6.1. Indexed Addressing with Literal Offset 9.6.2. Instructions Affected by Indexed Literal Offset Mode 9.6.3. Mapping the Access Bank in Indexed Literal Offset Mode 9.6.4. PIC18 Instruction Execution and the Extended Instruction Set 9.7. Register Definitions: Memory Organization 9.7.1. PCL 9.7.2. PCLAT 9.7.3. TOS 9.7.4. STKPTR 9.7.5. WREG 9.7.6. INDF 9.7.7. POSTDEC 9.7.8. POSTINC 9.7.9. PREINC 9.7.10. PLUSW 9.7.11. FSR 9.7.12. BSR 9.8. Register Summary - Memory Organization 10. NVM - Nonvolatile Memory Module 10.1. Operations 10.2. Unlock Sequence 10.3. Program Flash Memory (PFM) 10.3.1. Page Erase 10.3.2. Page Read 10.3.3. Word Read 10.3.4. Page Write 10.3.5. Word Write 10.3.6. Word Modify 10.3.7. Write Verify 10.3.8. Unexpected Termination of Write Operation 10.3.9. User ID, Device ID, Configuration Settings Access, DIA and DCI 10.3.10. Table Pointer Operations 10.3.10.1. Table Pointer Register 10.3.10.2. Table Latch Register 10.3.10.3. Table Read Operations 10.3.10.4. Table Write Operations 10.3.10.5. Table Pointer Boundaries 10.3.10.6. Reading the Program Flash Memory 10.4. Data Flash Memory (DFM) 10.4.1. Reading the DFM 10.4.2. Writing to DFM 10.4.3. Erasing the DFM 10.4.4. DFM Write Verify 10.4.5. Operation During Code-Protect and Write-Protect 10.4.6. Protection Against Spurious Writes 10.5. Register Definitions: NVM 10.5.1. NVMCON0 10.5.2. NVMCON1 10.5.3. NVMLOCK 10.5.4. NVMADR 10.5.5. NVMDAT 10.5.6. TBLPTR 10.5.7. TABLAT 10.6. Register Summary - NVM 11. VIC - Vectored Interrupt Controller Module 11.1. Overview 11.2. Interrupt Control and Status Registers 11.3. Interrupt Vector Table 11.3.1. Interrupt Vector Table Base Address (IVTBASE) 11.3.2. Interrupt Vector Table Contents 11.3.3. Interrupt Vector Table Address Calculation 11.3.4. Access Control for IVTBASE Registers 11.4. Interrupt Priority 11.4.1. User (Software) Priority 11.4.2. Natural Order (Hardware) Priority 11.5. Interrupt Operation 11.5.1. Serving a High- or Low-Priority Interrupt while the Main Routine Code is Executing 11.5.2. Serving a High-Priority Interrupt while a Low-Priority Interrupt is Pending 11.5.3. Preempting Low-Priority Interrupts 11.5.4. Simultaneous High- and Low-Priority Interrupts 11.6. Context Saving 11.6.1. Accessing Shadow Registers 11.7. Returning from Interrupt Service Routine (ISR) 11.8. Interrupt Latency 11.8.1. Aborting Interrupts 11.9. Interrupt Setup Procedure 11.10. External Interrupt Pins 11.11. Wake-up from Sleep 11.12. Interrupt Compatibility 11.13. Register Definitions: Interrupt Control 11.13.1. INTCON0 11.13.2. INTCON1 11.13.3. IVTBASE 11.13.4. IVTAD 11.13.5. IVTLOCK 11.13.6. SHADCON 11.13.7. PIE0 11.13.8. PIE1 11.13.9. PIE2 11.13.10. PIE3 11.13.11. PIE4 11.13.12. PIE5 11.13.13. PIE6 11.13.14. PIE7 11.13.15. PIE8 11.13.16. PIE9 11.13.17. PIE10 11.13.18. PIE11 11.13.19. PIE12 11.13.20. PIE13 11.13.21. PIE14 11.13.22. PIE15 11.13.23. PIR0 11.13.24. PIR1 11.13.25. PIR2 11.13.26. PIR3 11.13.27. PIR4 11.13.28. PIR5 11.13.29. PIR6 11.13.30. PIR7 11.13.31. PIR8 11.13.32. PIR9 11.13.33. PIR10 11.13.34. PIR11 11.13.35. PIR12 11.13.36. PIR13 11.13.37. PIR14 11.13.38. PIR15 11.13.39. IPR0 11.13.40. IPR1 11.13.41. IPR2 11.13.42. IPR3 11.13.43. IPR4 11.13.44. IPR5 11.13.45. IPR6 11.13.46. IPR7 11.13.47. IPR8 11.13.48. IPR9 11.13.49. IPR10 11.13.50. IPR11 11.13.51. IPR12 11.13.52. IPR13 11.13.53. IPR14 11.13.54. IPR15 11.14. Register Summary - Interrupts 12. OSC - Oscillator Module (With Fail-Safe Clock Monitor) 12.1. Clock Source Types 12.1.1. External Clock Sources 12.1.1.1. EC Mode 12.1.1.2. LP, XT, HS Modes 12.1.1.3. Oscillator Start-Up Timer (OST) 12.1.1.4. 4x PLL 12.1.1.5. Secondary Oscillator 12.1.1.5.1. SOSC Start-Up Timing 12.1.2. Internal Clock Sources 12.1.2.1. HFINTOSC 12.1.2.1.1. HFINTOSC Frequency Tuning 12.1.2.2. MFINTOSC 12.1.2.3. LFINTOSC 12.1.2.4. ADCRC 12.1.3. Oscillator Status and Manual Enable 12.2. Clock Switching 12.2.1. NOSC and NDIV Bits 12.2.2. COSC and CDIV Bits 12.2.3. CSWHOLD 12.2.4. PLL Input Switch 12.2.5. Clock Switch and Sleep 12.3. Fail-Safe Clock Monitor (FSCM) 12.3.1. Fail-Safe Detection 12.3.2. Fail-Safe Operation - FOSC Fail-Safe Clock Monitor 12.3.3. Fail-Safe Operation - Primary and Secondary Fail-Safe Clock Monitors 12.3.4. Fail-Safe Clock Monitor Fault Injection 12.3.5. Fail-Safe Condition Clearing 12.3.6. Reset or Wake-Up From Sleep 12.4. Active Clock Tuning (ACT) 12.4.1. ACT Lock Status 12.4.2. ACT Out-Of-Range Status 12.4.3. ACT Update Disable 12.4.4. ACT Interrupts 12.5. Register Definitions: Oscillator Module 12.5.1. ACTCON 12.5.2. OSCCON1 12.5.3. OSCCON2 12.5.4. OSCCON3 12.5.5. OSCTUNE 12.5.6. OSCFRQ 12.5.7. OSCSTAT 12.5.8. OSCEN 12.5.9. FSCMCON 12.6. Register Summary - Oscillator Module 13. CRC - Cyclic Redundancy Check Module with Memory Scanner 13.1. Module Overview 13.2. Polynomial Implementation 13.3. Data Sources 13.3.1. CRC from User Data 13.3.2. CRC from Flash 13.4. CRC Check Value 13.5. CRC Interrupt 13.6. Configuring the CRC Module 13.6.1. Register Overlay 13.7. Scanner Module Overview 13.8. Scanning Modes 13.8.1. TRIGEN = 0, BURSTMD = 0 13.8.2. TRIGEN = 1, BURSTMD = 0 13.8.3. TRIGEN = x, BURSTMD = 1 13.8.4. WWDT Interaction 13.9. Configuring the Scanner 13.10. Scanner Interrupt 13.11. Peripheral Module Disable 13.12. CRC-on-Boot Module Overview 13.12.1. Enabling the Module 13.12.2. Polynomial, Seed, and Expected Values 13.12.3. Memory Selection 13.12.4. Output Pin Setup 13.12.5. CRC Calculation 13.12.6. Mismatch Condition 13.13. Register Definitions: CRC and Scanner Control 13.13.1. CRCCON0 13.13.2. CRCCON1 13.13.3. CRCCON2 13.13.4. CRCDATA 13.13.5. CRCOUT 13.13.6. CRCSHIFT 13.13.7. CRCXOR 13.13.8. SCANCON0 13.13.9. SCANLADR 13.13.10. SCANHADR 13.13.11. SCANTRIG 13.13.12. BOOTREG 13.14. Register Summary - CRC 14. Resets 14.1. Power-on Reset (POR) 14.2. Brown-out Reset (BOR) 14.2.1. BOR is Always ON 14.2.2. BOR is OFF in Sleep 14.2.3. BOR Controlled by Software 14.2.4. BOR is always OFF 14.2.5. BOR and Bulk Erase 14.3. Low-Power Brown-out Reset (LPBOR) 14.3.1. Enabling LPBOR 14.3.2. LPBOR Module Output 14.4. MCLR Reset 14.4.1. MCLR Enabled 14.4.2. MCLR Disabled 14.5. Windowed Watchdog Timer (WWDT) Reset 14.6. RESET Instruction 14.7. Stack Overflow/Underflow Reset 14.8. Programming Mode Exit 14.9. Power-up Timer (PWRT) 14.10. Start-up Sequence 14.10.1. Memory Execution Violation 14.11. Determining the Cause of a Reset 14.12. Power Control (PCON0/PCON1) Registers 14.13. Register Definitions: Power Control 14.13.1. BORCON 14.13.2. PCON0 14.13.3. PCON1 14.14. Register Summary - BOR Control and Power Control 15. WWDT - Windowed Watchdog Timer 15.1. Independent Clock Source 15.2. WWDT Operating Modes 15.2.1. WWDT Is Always On 15.2.2. WWDT is Off in Sleep 15.2.3. WWDT Controlled by Software 15.3. Time-out Period 15.4. Watchdog Window 15.5. Clearing the Watchdog Timer 15.5.1. CLRWDT Considerations (Windowed Mode) 15.6. Operation During Sleep 15.7. Register Definitions: Windowed Watchdog Timer Control 15.7.1. WDTCON0 15.7.2. WDTCON1 15.7.3. WDTPSH 15.7.4. WDTPSL 15.7.5. WDTTMR 15.8. Register Summary: WDT Control 16. DMA - Direct Memory Access 16.1. DMA Registers 16.2. DMA Organization 16.3. DMA Interface 16.3.1. Special Function Registers with DMA Access only 16.3.2. DMA Addressing 16.3.3. DMA Message Size/Counters 16.3.4. DMA Message Transfers 16.3.4.1. Starting DMA Message Transfers 16.3.4.1.1. User Software Control 16.3.4.1.2. Hardware Trigger, SIRQ 16.3.4.2. Stopping DMA Message Transfers 16.3.4.2.1. User Software Control 16.3.4.2.2. Hardware Trigger, AIRQ 16.3.4.2.3. Source Count Reload 16.3.4.2.4. Destination Count Reload 16.3.4.2.5. Clearing the EN bit 16.4. Disable DMA Message Transfer Upon Completion 16.4.1. Clearing the SIRQEN bit 16.4.2. Source/Destination Stop 16.5. Types of Hardware Triggers 16.5.1. Edge Trigger Requests 16.5.2. Level Trigger Requests 16.6. Types of Data Transfers 16.7. DMA Interrupts 16.7.1. DMA Source Count Interrupt 16.7.2. DMA Destination Count Interrupt 16.7.3. Abort Interrupt 16.7.4. Overrun Interrupt 16.8. DMA Setup and Operation 16.8.1. Source Stop 16.8.2. Destination Stop 16.8.3. Continuous Transfer 16.8.4. Transfer from SFR to GPR 16.8.5. Overrun Condition 16.8.6. Abort Trigger, Message Complete 16.8.7. Abort Trigger, Message in Progress 16.9. Reset 16.10. Power-Saving Mode Operation 16.10.1. Sleep Mode 16.10.2. Idle Mode 16.10.3. Doze Mode 16.10.4. Peripheral Module Disable 16.11. Example Setup Code 16.12. Register Overlay 16.13. Register Definitions: DMA 16.13.1. DMASELECT 16.13.2. DMAnCON0 16.13.3. DMAnCON1 16.13.4. DMAnBUF 16.13.5. DMAnSSA 16.13.6. DMAnSSZ 16.13.7. DMAnSCNT 16.13.8. DMAnSPTR 16.13.9. DMAnDSA 16.13.10. DMAnDSZ 16.13.11. DMAnDCNT 16.13.12. DMAnDPTR 16.13.13. DMAnSIRQ 16.13.14. DMAnAIRQ 16.14. Register Summary - DMA 17. Power-Saving Modes 17.1. Doze Mode 17.1.1. Doze Operation 17.1.2. Interrupts During Doze 17.2. Sleep Mode 17.2.1. Wake-up from Sleep 17.2.2. Wake-up Using Interrupts 17.2.3. Low-Power Sleep Mode 17.2.3.1. Sleep Current vs. Wake-up Time 17.2.3.2. Peripheral Usage in Sleep 17.3. Idle Mode 17.3.1. Idle and Interrupts 17.3.2. Idle and WWDT 17.4. Peripheral Operation in Power-Saving Modes 17.5. Register Definitions: Power-Savings Control 17.5.1. CPUDOZE 17.5.2. VREGCON 17.6. Register Summary - Power-Savings Control 18. PMD - Peripheral Module Disable 18.1. Overview 18.2. Disabling a Module 18.3. Enabling a Module 18.4. Register Definitions: Peripheral Module Disable 18.4.1. PMD0 18.4.2. PMD1 18.4.3. PMD2 18.4.4. PMD3 18.4.5. PMD4 18.4.6. PMD5 18.4.7. PMD6 18.4.8. PMD7 18.4.9. PMD8 18.5. Register Summary - PMD 19. I/O Ports 19.1. Overview 19.2. PORTx - Data Register 19.3. LATx - Output Latch 19.4. TRISx - Direction Control 19.5. ANSELx - Analog Control 19.6. WPUx - Weak Pull-Up Control 19.7. INLVLx - Input Threshold Control 19.8. SLRCONx - Slew Rate Control 19.9. ODCONx - Open-Drain Control 19.10. Edge Selectable Interrupt-on-Change 19.11. I2C Pad Control 19.12. I/O Priorities 19.13. MCLR/VPP/RE3 Pin 19.14. Register Definitions: Port Control 19.14.1. PORTx 19.14.2. LATx 19.14.3. TRISx 19.14.4. ANSELx 19.14.5. WPUx 19.14.6. INLVLx 19.14.7. SLRCONx 19.14.8. ODCONx 19.14.9. RxyI2C 19.15. Register Summary - IO Ports 20. IOC - Interrupt-on-Change 20.1. Overview 20.2. Enabling the Module 20.3. Individual Pin Configuration 20.4. Interrupt Flags 20.5. Clearing Interrupt Flags 20.6. Operation in Sleep 20.7. Register Definitions: Interrupt-on-Change Control 20.7.1. IOCxF 20.7.2. IOCxN 20.7.3. IOCxP 20.8. Register Summary: Interrupt-on-Change Control 21. PPS - Peripheral Pin Select Module 21.1. Overview 21.2. PPS Inputs 21.3. PPS Outputs 21.4. Bidirectional Pins 21.5. PPS Lock 21.5.1. PPS One-Way Lock 21.6. Operation During Sleep 21.7. Effects of a Reset 21.8. Register Definitions: Peripheral Pin Select (PPS) 21.8.1. xxxPPS 21.8.2. RxyPPS 21.8.3. PPSLOCK 21.9. Register Summary: Peripheral Pin Select Module 21.9.1. CANRXPPS 22. CLC - Configurable Logic Cell 22.1. CLC Setup 22.1.1. Data Selection 22.1.2. Data Gating 22.1.3. Logic Function 22.1.4. Output Polarity 22.2. CLC Interrupts 22.3. Effects of a Reset 22.4. Output Mirror Copies 22.5. Operation During Sleep 22.6. CLC Setup Steps 22.7. Register Overlay 22.8. Register Definitions: Configurable Logic Cell 22.8.1. CLCSELECT 22.8.2. CLCnCON 22.8.3. CLCnPOL 22.8.4. CLCnSEL0 22.8.5. CLCnSEL1 22.8.6. CLCnSEL2 22.8.7. CLCnSEL3 22.8.8. CLCnGLS0 22.8.9. CLCnGLS1 22.8.10. CLCnGLS2 22.8.11. CLCnGLS3 22.8.12. CLCDATA 22.9. Register Summary - CLC Control 23. CLKREF - Reference Clock Output Module 23.1. Clock Source 23.1.1. Clock Synchronization 23.2. Programmable Clock Divider 23.3. Selectable Duty Cycle 23.4. Operation in Sleep Mode 23.5. Register Definitions: Reference Clock 23.5.1. CLKRCON 23.5.2. CLKRCLK 23.6. Register Summary: Reference CLK 24. TMR0 - Timer0 Module 24.1. Timer0 Operation 24.1.1. 8-Bit Mode 24.1.2. 16-Bit Mode 24.2. Clock Selection 24.2.1. Synchronous Mode 24.2.2. Asynchronous Mode 24.2.3. Programmable Prescaler 24.2.4. Programmable Postscaler 24.3. Timer0 Output and Interrupt 24.3.1. Timer0 Output 24.3.2. Timer0 Interrupt 24.3.3. Timer0 Example 24.4. Operation During Sleep 24.5. Register Definitions: Timer0 Control 24.5.1. T0CON0 24.5.2. T0CON1 24.5.3. TMR0H 24.5.4. TMR0L 24.6. Register Summary: Timer0 25. TMR1 - Timer1 Module with Gate Control 25.1. Timer1 Operation 25.2. Clock Source Selection 25.2.1. Internal Clock Source 25.2.2. External Clock Source 25.3. Timer1 Prescaler 25.4. Secondary Oscillator 25.5. Timer1 Operation in Asynchronous Counter Mode 25.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 25.6. Timer1 16-Bit Read/Write Mode 25.7. Timer1 Gate 25.7.1. Timer1 Gate Enable 25.7.2. Timer1 Gate Source Selection 25.7.3. Timer1 Gate Toggle Mode 25.7.4. Timer1 Gate Single Pulse Mode 25.7.5. Timer1 Gate Value Status 25.7.6. Timer1 Gate Event Interrupt 25.8. Timer1 Interrupt 25.9. Timer1 Operation During Sleep 25.10. CCP Capture/Compare Time Base 25.11. CCP Special Event Trigger 25.12. Peripheral Module Disable 25.13. Register Definitions: Timer1 Control 25.13.1. TxCON 25.13.2. TxGCON 25.13.3. TxCLK 25.13.4. TxGATE 25.13.5. TMRx 25.14. Register Summary Timer 1 26. TMR2 - Timer2 Module 26.1. Timer2 Operation 26.1.1. Free-Running Period Mode 26.1.2. One-Shot Mode 26.1.3. Monostable Mode 26.2. Timer2 Output 26.3. External Reset Sources 26.4. Timer2 Interrupt 26.5. PSYNC bit 26.6. CSYNC bit 26.7. Operating Modes 26.8. Operation Examples 26.8.1. Software Gate Mode 26.8.2. Hardware Gate Mode 26.8.3. Edge-Triggered Hardware Limit Mode 26.8.4. Level-Triggered Hardware Limit Mode 26.8.5. Software Start One-Shot Mode 26.8.6. Edge-Triggered One-Shot Mode 26.8.7. Edge-Triggered Hardware Limit One-Shot Mode 26.8.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 26.8.9. Edge-Triggered Monostable Modes 26.8.10. Level-Triggered Hardware Limit One-Shot Modes 26.9. Timer2 Operation During Sleep 26.10. Register Definitions: Timer2 Control 26.10.1. TxTMR 26.10.2. TxPR 26.10.3. TxCON 26.10.4. TxHLT 26.10.5. TxCLKCON 26.10.6. TxRST 26.11. Register Summary - Timer2 27. SMT - Signal Measurement Timer 27.1. SMT Operation 27.1.1. Clock Source Selection 27.1.2. Signal and Window Source Selection 27.1.3. Time Base 27.1.4. Pulse Width and Period Captures 27.1.5. Status Information 27.1.6. Modes of Operation 27.1.6.1. Timer Mode 27.1.6.2. Gated Timer Mode 27.1.6.3. Period and Duty Cycle Measurement Mode 27.1.6.4. High and Low Measurement Mode 27.1.6.5. Windowed Measurement Mode 27.1.6.6. Gated Window Measurement Mode 27.1.6.7. Time-of-Flight Measurement Mode 27.1.6.8. Capture Mode 27.1.6.9. Counter Mode 27.1.6.10. Gated Counter Mode 27.1.6.11. Windowed Counter Mode 27.1.7. Interrupts 27.1.8. Operation During Sleep 27.2. Register Definitions: SMT Control 27.2.1. SMTxCON0 27.2.2. SMTxCON1 27.2.3. SMTxSTAT 27.2.4. SMTxCLK 27.2.5. SMTxWIN 27.2.6. SMTxSIG 27.2.7. SMTxTMR 27.2.8. SMTxCPR 27.2.9. SMTxCPW 27.2.10. SMTxPR 27.3. Register Summary - SMT Control 28. UTMR - Universal Timer Module 28.1. Module Nomenclature 28.2. Clock Source Selection 28.3. UTMR Prescaler 28.4. UTMR Operation 28.4.1. Synchronous vs. Asynchronous Operation 28.4.2. Timer Counter and Capture Registers 28.4.3. Timer Period Register 28.4.4. External Reset Source (ERS) 28.4.5. Start, Stop and Reset Events 28.4.5.1. Start Event 28.4.5.2. Reset Event 28.4.5.3. Stop Event 28.4.6. Hardware Limit Mode 28.4.7. One-Shot Mode 28.4.8. Run Status Flag 28.5. UTMR Output Modes 28.6. Interrupt and DMA Triggers 28.7. Operation During Sleep 28.8. Chaining Counter Timers 28.9. Register Definitions: Universal Timer 28.9.1. TUxyCON0 28.9.2. TUxyCON1 28.9.3. TUxyHLT 28.9.4. TUxyPS 28.9.5. TUxyTMR (16-bit) 28.9.6. TUxyCR (16-bit) 28.9.7. TUxyPR (16-bit) 28.9.8. TUxyCLK 28.9.9. TUxyERS 28.9.10. TUCHAIN 28.10. Register Summary - Universal Timer 29. CCP - Capture/Compare/PWM Module 29.1. CCP Module Configuration 29.1.1. CCP Modules and Timer Resources 29.1.2. Open-Drain Output Option 29.2. Capture Mode 29.2.1. Capture Sources 29.2.2. Timer1 Mode for Capture 29.2.3. Software Interrupt Mode 29.2.4. CCP Prescaler 29.2.5. Capture During Sleep 29.3. Compare Mode 29.3.1. CCPx Pin Configuration 29.3.2. Timer1 Mode for Compare 29.3.3. Compare During Sleep 29.4. PWM Overview 29.4.1. Standard PWM Operation 29.4.2. Setup for PWM Operation 29.4.3. Timer2 Timer Resource 29.4.4. PWM Period 29.4.5. PWM Duty Cycle 29.4.6. PWM Resolution 29.4.7. Operation in Sleep Mode 29.4.8. Changes in System Clock Frequency 29.4.9. Effects of Reset 29.5. Register Definitions: CCP Control 29.5.1. CCPxCON 29.5.2. CCPxCAP 29.5.3. CCPRx 29.6. Register Summary - CCP Control 30. Capture, Compare, and PWM Timers Selection 30.1. Register Definitions: Capture, Compare, and PWM Timer Selection 30.1.1. CCPTMRS0 30.2. Register Summary - Capture, Compare, and PWM Timers Selection 31. PWM - Pulse-Width Modulator with Compare 31.1. Output Slices 31.1.1. Output Polarity 31.1.2. Operating Modes 31.1.2.1. Left Aligned Mode 31.1.2.2. Right Aligned Mode 31.1.2.3. Center Aligned Mode 31.1.2.4. Variable Alignment Mode 31.1.2.5. Compare Modes 31.1.2.5.1. Pulsed Compare Mode 31.1.2.5.2. Toggled Compare 31.1.3. Push-Pull Mode 31.2. Period Timer 31.3. Clock Sources 31.3.1. Clock Prescaler 31.4. External Period Resets 31.5. Buffered Period and Parameter Registers 31.6. Synchronizing Multiple PWMs 31.7. Interrupts 31.7.1. Period Interrupt 31.7.1.1. Period Interrupt Postscaler 31.7.2. Parameter Interrupts 31.8. Operation During Sleep 31.9. Register Definitions: PWM Control 31.9.1. PWMxERS 31.9.2. PWMxCLK 31.9.3. PWMxLDS 31.9.4. PWMxPR 31.9.5. PWMxCPRE 31.9.6. PWMxPIPOS 31.9.7. PWMxGIR 31.9.8. PWMxGIE 31.9.9. PWMxCON 31.9.10. PWMxSaCFG 31.9.11. PWMxSaP1 31.9.12. PWMxSaP2 31.9.13. PWMLOAD 31.9.14. PWMEN 31.10. Register Summary - PWM 32. CWG - Complementary Waveform Generator Module 32.1. Fundamental Operation 32.2. Operating Modes 32.2.1. Half-Bridge Mode 32.2.2. Push-Pull Mode 32.2.3. Full-Bridge Mode 32.2.3.1. Direction Change in Full-Bridge Mode 32.2.3.2. Dead-Band Delay in Full-Bridge Mode 32.2.4. Steering Modes 32.2.4.1. Synchronous Steering Mode 32.2.4.2. Asynchronous Steering Mode 32.2.4.3. Start-up Considerations 32.3. Clock Source 32.4. Selectable Input Sources 32.5. Output Control 32.5.1. CWG Output 32.5.2. Polarity Control 32.6. Dead-Band Control 32.6.1. Dead-Band Functionality In Half-Bridge Mode 32.6.2. Dead-Band Functionality In Full-Bridge Mode 32.7. Rising Edge and Reverse Dead-Band 32.8. Falling Edge and Forward Dead Band 32.9. Dead-Band Jitter 32.10. Auto-Shutdown 32.10.1. Shutdown 32.10.2. Software Generated Shutdown 32.10.3. External Input Source 32.10.4. Pin Override Levels 32.10.5. Auto-Shutdown Interrupts 32.11. Auto-Shutdown Restart 32.11.1. Software-Controlled Restart 32.11.2. Auto-Restart 32.12. Operation During Sleep 32.13. Configuring the CWG 32.14. Register Definitions: CWG Control 32.14.1. CWGxCON0 32.14.2. CWGxCON1 32.14.3. CWGxCLK 32.14.4. CWGxISM 32.14.5. CWGxSTR 32.14.6. CWGxAS0 32.14.7. CWGxAS1 32.14.8. CWGxDBR 32.14.9. CWGxDBF 32.15. Register Summary - CWG 33. NCO - Numerically Controlled Oscillator Module 33.1. NCO Operation 33.1.1. NCO Clock Sources 33.1.2. Accumulator 33.1.3. Adder 33.1.4. Increment Registers 33.2. Fixed Duty Cycle Mode 33.3. Pulse Frequency Mode 33.4. Output Polarity Control 33.5. Interrupts 33.6. Effects of a Reset 33.7. Operation in Sleep 33.8. Register Definitions: NCO 33.8.1. NCOxCON 33.8.2. NCOxCLK 33.8.3. NCOxACC 33.8.4. NCOxINC 33.9. Register Summary - NCO 34. DSM - Data Signal Modulator Module 34.1. DSM Operation 34.1.1. Modulator Signal Sources 34.1.2. Carrier Signal Sources 34.2. Carrier Synchronization 34.3. Carrier Source Polarity Select 34.4. Programmable Modulator Data 34.5. Modulated Output Polarity 34.6. Operation in Sleep Mode 34.7. Effects of a Reset 34.8. Peripheral Module Disable 34.9. Register Definitions: Modulation Control 34.9.1. MDxCON0 34.9.2. MDxCON1 34.9.3. MDxCARH 34.9.4. MDxCARL 34.9.5. MDxSRC 34.10. Register Summary - DSM 35. UART - Universal Asynchronous Receiver Transmitter with Protocol Support 35.1. UART I/O Pin Configuration 35.2. UART Asynchronous Modes 35.2.1. UART Asynchronous Transmitter 35.2.1.1. Enabling the Transmitter 35.2.1.2. Transmitting Data 35.2.1.3. Transmit Data Polarity 35.2.1.4. Transmit Interrupt Flag 35.2.1.5. TSR Status 35.2.1.6. Transmitter 7-bit Mode 35.2.1.7. Transmitter Parity Modes 35.2.1.8. Asynchronous Transmission Setup 35.2.2. UART Asynchronous Receiver 35.2.2.1. Enabling the Receiver 35.2.2.2. Receiving Data 35.2.2.3. Receive Data Polarity 35.2.2.4. Receive Interrupts 35.2.2.5. Receive Framing Error 35.2.2.6. Receiver Parity Modes 35.2.2.7. Receive FIFO Overflow 35.2.2.8. Asynchronous Reception Setup 35.2.3. Asynchronous Address Mode 35.2.3.1. Address Mode Transmit 35.2.3.2. Address Mode Receive 35.3. DMX Mode (Full-featured UARTs only) 35.3.1. DMX Controller 35.3.2. DMX Receiver 35.4. LIN Modes (Full-featured UARTs only) 35.4.1. LIN Master/Slave Mode 35.4.2. LIN Slave Mode 35.4.2.1. LIN Slave Receiver 35.4.2.2. LIN Slave Transmitter 35.5. DALI Mode (Full-featured UARTs only) 35.5.1. Control Device 35.5.2. Control Gear 35.6. General Purpose Manchester (Full-featured UARTs only) 35.7. Polarity 35.8. Stop Bits 35.8.1. Delayed Receive Interrupt 35.9. Operation After FIFO Overflow 35.10. Receive and Transmit Buffers 35.10.1. FIFO Status 35.10.2. FIFO Reset 35.11. Flow Control 35.11.1. Hardware Flow Control 35.11.2. RS-485 Transceiver Control 35.11.3. XON/XOFF Flow Control 35.12. Checksum (Full-featured UARTs only) 35.12.1. Transmit Checksum Method 35.12.2. Receive Checksum Method 35.13. Collision Detection (Full-featured UARTs only) 35.14. RX/TX Activity Time-out 35.15. Clock Accuracy With Asynchronous Operation 35.16. UART Baud Rate Generator 35.16.1. Auto-Baud Detect 35.16.2. Auto-Baud Overflow 35.16.3. Auto Wake-on-Break 35.16.3.1. Auto Wake-Up Special Considerations 35.17. Transmitting a Break 35.18. Receiving a Break 35.19. UART Operation During Sleep 35.20. Register Definitions: UART 35.20.1. UxCON0 35.20.2. UxCON1 35.20.3. UxCON2 35.20.4. UxERRIR 35.20.5. UxERRIE 35.20.6. UxUIR 35.20.7. UxFIFO 35.20.8. UxBRG 35.20.9. UxRXB 35.20.10. UxTXB 35.20.11. UxP1 35.20.12. UxP2 35.20.13. UxP3 35.20.14. UxTXCHK 35.20.15. UxRXCHK 35.21. Register Summary - UART 36. SPI - Serial Peripheral Interface Module 36.1. SPI Controls 36.2. SPI Operation 36.2.1. Enabling and Disabling the SPI Module 36.2.2. BUSY Bit 36.2.3. Transmit and Receive FIFOs 36.2.4. LSb vs. MSb-First Operation 36.2.5. Input and Output Polarity Control 36.2.6. Transfer Counter 36.2.6.1. Total Bit Count Mode (BMODE = 0) 36.2.6.2. Variable Transfer Size Mode (BMODE = 1) 36.2.6.3. Transfer Counter in Slave Mode 36.3. Master Mode 36.3.1. Full-Duplex Mode 36.3.2. Transmit Only Mode 36.3.3. Receive Only Mode 36.3.4. Transfer Off Mode 36.3.5. Master Mode Slave Select Control 36.3.5.1. Hardware Slave Select Control 36.3.5.2. Software Slave Select Control 36.3.6. Master Mode SPI Clock Configuration 36.3.6.1. SPI Clock Selection 36.3.6.2. Clock and Data Change Alignment 36.3.6.3. SCK Start-up Delay 36.4. Slave Mode 36.4.1. Slave Mode Transmit Options 36.4.1.1. SDO Drive/Tri-state 36.4.1.2. SDO Output Data 36.4.2. Slave Mode Receive Options 36.4.3. Slave Mode Slave Select 36.4.4. Slave Mode Clock Configuration 36.4.5. Daisy-Chain Configuration 36.5. SPI Operation In Sleep Mode 36.6. SPI Interrupts 36.6.1. SPI Receive Interrupt 36.6.2. SPI Transmit Interrupt 36.6.3. SPI Status Interrupts 36.6.3.1. Shift Register Empty Interrupt 36.6.3.2. Transfer Counter is Zero Interrupt 36.6.3.3. Start of Slave Select and End of Slave Select Interrupts 36.6.3.4. Receiver Overflow and Transmitter Underflow Interrupts 36.7. Register Definitions: Serial Peripheral Interface 36.7.1. SPIxCON0 36.7.2. SPIxCON1 36.7.3. SPIxCON2 36.7.4. SPIxCLK 36.7.5. SPIxBAUD 36.7.6. SPIxTCNT 36.7.7. SPIxTWIDTH 36.7.8. SPIxSTATUS 36.7.9. SPIxRXB 36.7.10. SPIxTXB 36.7.11. SPIxINTE 36.7.12. SPIxINTF 36.8. Register Summary - SPI Control 37. I2C - Inter-Integrated Circuit Module 37.1. I2C Features 37.2. I2C Terminology 37.3. I2C Module Overview 37.3.1. Byte Format 37.3.2. SDA and SCL Pins 37.3.2.1. SDA Hold Time 37.3.3. Start Condition 37.3.4. Acknowledge Sequence 37.3.5. Restart Condition 37.3.6. Stop Condition 37.3.7. Bus Timeout 37.3.8. Address Buffers 37.3.9. Transmit Buffer 37.3.10. Receive Buffer 37.3.11. Clock Stretching 37.3.11.1. Clock Stretching for Buffer Operations 37.3.11.2. Clock Stretching for Other Slave Operations 37.3.12. Data Byte Count 37.3.12.1. Auto-Load I2CxCNT 37.3.13. DMA Integration 37.3.13.1. 7-Bit Master Transmission 37.3.13.2. 10-Bit Master Transmission 37.3.13.3. 7/10-Bit Master Reception 37.3.13.4. 7-Bit Slave Transmission 37.3.13.5. 10-Bit Slave Transmission 37.3.13.6. 7/10-Bit Slave Reception 37.3.14. Interrupts 37.3.14.1. High-Level Interrupts 37.3.14.2. Condition-Specific Interrupts 37.3.15. Operation in Sleep 37.4. I2C Operation 37.4.1. I2C Slave Mode Operation 37.4.1.1. Slave Addressing Modes 37.4.1.2. General Call Addressing Support 37.4.1.3. Slave Operation in 7-Bit Addressing Modes 37.4.1.3.1. Slave Transmission (7-bit Addressing Mode) 37.4.1.3.2. Slave Reception (7-Bit Addressing Mode) 37.4.1.4. Slave Operation in 10-Bit Addressing Modes 37.4.1.4.1. Slave Transmission (10-Bit Addressing Mode) 37.4.1.4.2. Slave Reception (10-Bit Addressing Mode) 37.4.2. I2C Master Mode Operation 37.4.2.1. Bus Free Time 37.4.2.2. Master Clock Timing 37.4.2.3. Start Condition Timing 37.4.2.4. Acknowledge Sequence Timing 37.4.2.5. Restart Condition Timing 37.4.2.6. Stop Condition Timing 37.4.2.7. Master Operation in 7-Bit Addressing Modes 37.4.2.7.1. Master Transmission (7-Bit Addressing Mode) 37.4.2.7.2. Master Reception (7-Bit Addressing Mode) 37.4.2.8. Master Operation in 10-Bit Addressing Modes 37.4.2.8.1. Master Transmission (10-Bit) 37.4.2.8.2. Master Reception (10-Bit Addressing Mode) 37.4.3. I2C Multi-Master Mode Operation 37.4.3.1. Multi-Master Mode Clock Synchronization 37.4.3.2. Multi-Master Mode Bus Arbitration 37.5. Register Definitions: I2C Control 37.5.1. I2CxCON0 37.5.2. I2CxCON1 37.5.3. I2CxCON2 37.5.4. I2CxSTAT0 37.5.5. I2CxSTAT1 37.5.6. I2CxPIR 37.5.7. I2CxPIE 37.5.8. I2CxERR 37.5.9. I2CxCLK 37.5.10. I2CxBAUD 37.5.11. I2CxCNT 37.5.12. I2CxBTO 37.5.13. I2CxBTOC 37.5.14. [I2CxADB0] 37.5.15. I2CxADB1 37.5.16. I2CxADR0 37.5.17. I2CxADR1 37.5.18. I2CxADR2 37.5.19. I2CxADR3 37.5.20. I2CxTXB 37.5.21. I2CxRXB 37.6. Register Summary - I2C 38. CAN FD - Controller Area Network, Flexible Data-Rate 38.1. Module Overview 38.1.1. Module Functionality 38.2. Modes of Operation 38.2.1. Mode Change 38.2.1.1. Changing Between Normal Modes 38.2.1.2. Changing Between Debug Modes 38.2.1.3. Exiting Normal Mode 38.2.1.4. Entering and Exiting Disable Mode 38.2.1.5. Bus Integrating Mode 38.2.2. Configuration Mode 38.2.3. Normal Modes 38.2.3.1. Normal CAN FD Mode 38.2.3.2. Normal CAN 2.0 Mode 38.2.4. Disable Mode 38.2.5. Debug Modes 38.2.5.1. Listen Only Mode 38.2.5.2. Restricted Operation Mode 38.2.5.3. Loopback Mode 38.2.5.3.1. Internal Loopback Mode 38.2.5.3.2. External Loopback Mode 38.2.6. Low-Power Modes 38.2.6.1. Sleep Mode 38.2.6.2. Idle Mode 38.2.6.3. Wake-Up From Sleep 38.3. Configuration 38.3.1. Clock Configuration 38.3.2. CAN Configuration 38.3.2.1. ISO CRC Enable 38.3.2.2. Protocol Exception Disable 38.3.2.3. Wake-up Filter 38.3.2.4. Restriction of Transmission Attempts 38.3.2.5. Error State Indicator (ESI) in Gateway Mode 38.3.2.6. Mode Selection In Case of System Error 38.3.2.7. Reserving Message Memory for TXQ and TEF 38.3.3. CAN FD Bit Time Configuration 38.3.3.1. Sample Point 38.3.3.2. Propagation Delay 38.3.3.3. Transmitter Delay Compensation (TDC) 38.3.3.4. Synchronization 38.3.3.5. Synchronization Jump Width 38.3.3.6. Oscillator Tolerance 38.3.3.7. Recommendations for Bit Time Configuration 38.3.3.8. Bit Time Configuration Example 38.3.4. Message Memory Configuration 38.3.4.1. Transmit Event FIFO Configuration 38.3.4.2. Transmit Queue Configuration 38.3.4.3. Transmit FIFO Configuration 38.3.4.4. Receive FIFO Configuration 38.3.4.5. Calculation of Required Message Memory 38.4. CAN FD Message Frames 38.4.1. ISO vs. Non-ISO CRC 38.4.1.1. DLC Encoding 38.5. Message Transmission 38.5.1. Transmit Message Object 38.5.2. Loading Messages into Transmit FIFO 38.5.3. Loading Messages Into Transmit Queue 38.5.4. Requesting Transmission of Message in Transmit FIFO 38.5.5. Requesting Transmission of Message in Transmit Queue 38.5.6. C1TXREQ Register 38.5.7. Transmit Priority 38.5.7.1. Transmit Priority of Messages in FIFO 38.5.7.2. Transmit Priority of Messages in TXQ 38.5.7.3. Transmit Priority Based on ID 38.5.8. Transmit Bandwidth Sharing 38.5.9. Retransmission Attempts 38.5.9.1. Retransmission Attempts Disabled 38.5.9.2. Three Retransmission Attempts 38.5.9.3. Unlimited Retransmission 38.5.10. Aborting Transmission 38.5.11. Remote Transmit Request (RTR) 38.5.12. Mismatch of DLC and Payload Size During Transmission 38.5.13. Transmit State Diagram 38.5.14. Resetting Transmit FIFO 38.5.15. Resetting Transmit Queue 38.6. Transmit Event FIFO (TEF) 38.6.1. Reading a TEF Object 38.6.1.1. Resetting the TEF 38.7. Message Filtering 38.7.1. Filter Configuration 38.7.2. Filtering a Received Message 38.7.2.1. Filtering Standard or Extended Frames 38.7.2.2. Mask Bits 38.7.2.3. Filtering on Data Bytes 38.7.2.4. 12-Bit Standard ID 38.8. Message Reception 38.8.1. Receive Message Object 38.8.1.1. Reading a Receive Message Object 38.8.2. Receive State Diagram 38.8.3. Resetting RX FIFO 38.8.4. Mismatch of DLC and Payload Size During Reception 38.9. FIFO Behavior 38.9.1. FIFO Status Flags 38.9.1.1. TX FIFO Status Flags 38.9.1.2. RX FIFO Status Flags 38.9.1.3. TXQ Status Flags 38.9.1.4. TEF Status Flags 38.9.2. Transmit FIFO Behavior 38.9.3. Receive FIFO Behavior 38.9.4. Transmit Queue Behavior 38.9.5. Transmit Event FIFO Behavior 38.10. Timestamping 38.11. Interrupts 38.11.1. FIFO Individual Interrupts 38.11.1.1. Transmit Queue Interrupts 38.11.1.2. Receive FIFO Interrupts (RFIF) 38.11.1.3. Transmit FIFO Interrupts (TFIF) 38.11.1.4. Receive FIFO Overrun Interrupt (RXOVIF) 38.11.1.5. Transmit FIFO Attempt Interrupt (TXATIF) 38.11.1.6. Transmit Event FIFO Interrupts (TEFIF) 38.11.2. FIFO Combined Interrupts 38.11.3. Main Interrupts 38.11.3.1. Invalid Message Interrupt - IVMIF 38.11.3.2. Wake-Up Interrupt (WAKIF) 38.11.3.3. CAN Bus Error Interrupt (CERRIF) 38.11.3.4. CAN Mode Change Interrupt (MODIF) 38.11.3.5. CAN Timer Interrupt (TBCIF) 38.11.3.6. System Error Interrupt (SERRIF) 38.11.4. Interrupt Handling 38.11.4.1. Interrupt Look-up Table 38.11.4.2. Interrupt Status Register 38.11.5. Interrupt Flags 38.12. Error Handling 38.12.1. Bus Diagnostic Registers 38.12.2. Recovery from Bus Off State 38.13. Register Definitions: CAN FD Control 38.13.1. CxCON 38.13.2. CxNBTCFG 38.13.3. CxDBTCFG 38.13.4. CxTDC 38.13.5. CxTBC 38.13.6. CxTSCON 38.13.7. CxVEC 38.13.8. CxINT 38.13.9. CxRXIF 38.13.10. CxTXIF 38.13.11. CxRXOVIF 38.13.12. CxTXATIF 38.13.13. CxTXREQ 38.13.14. CxTREC 38.13.15. CxBDIAG0 38.13.16. CxBDIAG1 38.13.17. CxTEFCON 38.13.18. CxTEFSTA 38.13.19. CxTEFUA 38.13.20. CxFIFOBA 38.13.21. CxTXQCON 38.13.22. CxTXQSTA 38.13.23. CxTXQUA 38.13.24. CxFIFOCONy 38.13.25. CxFIFOSTAy 38.13.26. CxFIFOUAy 38.13.27. CxFLTCON0 38.13.28. CxFLTCON1 38.13.29. CxFLTCON2 38.13.30. CxFLTOBJy 38.13.31. CxMASKy 38.14. Register Summary - CAN FD 39. JTAG Boundary Scan 39.1. Test Access Port (TAP) and TAP Controller 39.1.1. TAP 39.1.2. TAP Controller 39.2. JTAG Registers 39.2.1. Instruction Shift Register and Instruction Register 39.2.2. Data Registers 39.3. Boundary Scan Register (BSR) 39.3.1. Boundary Scan Cell (BSC) 39.4. JTAG Instructions 39.5. Boundary Scan Testing 39.5.1. Related JTAG Files 39.6. Effects of Reset 40. HLVD - High/Low-Voltage Detect 40.1. Operation 40.2. Setup 40.3. Current Consumption 40.4. HLVD Start-up Time 40.5. Applications 40.6. Operation During Sleep 40.7. Operation During Idle and Doze Modes 40.8. Effects of a Reset 40.9. Register Definitions: HLVD Control 40.9.1. HLVDCON0 40.9.2. HLVDCON1 40.10. Register Summary - HLVD 41. FVR - Fixed Voltage Reference 41.1. Independent Gain Amplifiers 41.2. FVR Stabilization Period 41.3. Register Definitions: FVR 41.3.1. FVRCON 41.4. Register Summary - FVR 42. Temperature Indicator Module 42.1. Module Operation 42.1.1. Temperature Indicator Range 42.1.2. Minimum Operating VDD 42.2. Temperature Calculation 42.2.1. Higher-Order Calibration 42.3. ADC Acquisition Time 42.4. Register Definitions: Temperature Indicator 42.4.1. FVRCON 42.5. Register Summary - Temperature Indicator 43. ADC - Analog-to-Digital Converter with Computation and Context Module 43.1. ADC Configuration 43.1.1. Port Configuration 43.1.2. Channel Selection 43.1.3. ADC Voltage Reference 43.1.4. Conversion Clock 43.1.5. Interrupts 43.1.6. Result Formatting 43.2. ADC Operation 43.2.1. Starting a Conversion 43.2.2. Completion of a Conversion 43.2.3. ADC Operation During Sleep 43.2.4. External Trigger During Sleep 43.2.5. Auto-Conversion Trigger 43.2.6. ADC Conversion Procedure (Basic Mode) 43.3. ADC Acquisition Requirements 43.4. ADC Charge Pump 43.5. Computation Operation 43.5.1. Digital Filter/Average 43.5.2. Basic Mode 43.5.3. Accumulate Mode 43.5.4. Average Mode 43.5.5. Burst Average Mode 43.5.6. Low-Pass Filter Mode 43.5.7. Threshold Comparison 43.5.8. Repetition and Sampling Options 43.5.8.1. Continuous Sampling Mode 43.5.8.2. Double Sample Conversion 43.5.9. Capacitive Voltage Divider (CVD) Features 43.5.9.1. CVD Operation 43.5.9.2. Precharge Control 43.5.9.3. Acquisition Control for CVD (ADPRE > 0) 43.5.9.4. Guard Ring Outputs 43.5.9.5. Additional Sample-and-Hold Capacitance 43.6. Channel Sequencer and Context 43.6.1. Channel Context 43.6.1.1. Channel Context Configuration 43.6.1.2. Channel Context Configuration Example 43.6.2. Channel Sequencer 43.6.2.1. DMA Access 43.6.2.2. Channel Sequencer Configuration Examples 43.7. Register Definitions: ADC Control 43.7.1. ADCON0 43.7.2. ADCON1 43.7.3. ADCON2 43.7.4. ADCON3 43.7.5. ADSTAT 43.7.6. ADCLK 43.7.7. ADREF 43.7.8. ADPCH 43.7.9. ADPRE 43.7.10. ADACQ 43.7.11. ADCAP 43.7.12. ADRPT 43.7.13. ADCNT 43.7.14. ADFLTR 43.7.15. ADRES 43.7.16. ADPREV 43.7.17. ADACC 43.7.18. ADSTPT 43.7.19. ADERR 43.7.20. ADLTH 43.7.21. ADUTH 43.7.22. ADACT 43.7.23. ADCP 43.7.24. ADCTX 43.7.25. ADCSELx 43.8. Register Summary - ADC 44. DAC - Digital-to-Analog Converter Module 44.1. Output Voltage Selection 44.2. Ratiometric Output Level 44.3. Operation During Sleep 44.4. Effects of a Reset 44.5. Register Definitions: DAC Control 44.5.1. DACxCON 44.5.2. DACxDATL 44.6. Register Summary - DAC 45. CMP - Comparator Module 45.1. Comparator Overview 45.2. Comparator Control 45.2.1. Comparator Enable 45.2.2. Comparator Output 45.2.3. Comparator Output Polarity 45.3. Comparator Output Synchronization 45.4. Comparator Hysteresis 45.5. Comparator Interrupt 45.6. Comparator Positive Input Selection 45.7. Comparator Negative Input Selection 45.8. Comparator Response Time 45.9. Analog Input Connection Considerations 45.10. Operation in Sleep Mode 45.11. ADC Auto-Trigger Source 45.12. Register Definitions: Comparator Control 45.12.1. CMxCON0 45.12.2. CMxCON1 45.12.3. CMxNCH 45.12.4. CMxPCH 45.12.5. CMOUT 45.13. Register Summary - Comparator 46. ZCD - Zero-Cross Detection Module 46.1. External Resistor Selection 46.2. ZCD Logic Output 46.3. ZCD Logic Polarity 46.4. ZCD Interrupts 46.5. Correction for ZCPINV Offset 46.5.1. Correction by AC Coupling 46.5.2. Correction By Offset Current 46.6. Handling VPEAK Variations 46.7. Operation During Sleep 46.8. Effects of a Reset 46.9. Disabling the ZCD Module 46.10. Register Summary: ZCD 46.11. Register Definitions: ZCD Control 46.11.1. ZCDCON 47. Instruction Set Summary 47.1. Standard Instruction Set 47.1.1. Standard Instruction Set 47.2. Extended Instruction Set 47.2.1. Extended Instruction Syntax 47.2.2. Extended Instruction Set 47.2.3. Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 47.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 47.2.4. Considerations when Enabling the Extended Instruction Set 47.2.5. Special Considerations with Microchip MPLAB® IDE Tools 48. ICSP™ - In-Circuit Serial Programming™ 48.1. High-Voltage Programming Entry Mode 48.2. Low-Voltage Programming Entry Mode 48.3. Common Programming Interfaces 49. Register Summary 50. Electrical Specifications 50.1. Absolute Maximum Ratings(†) 50.2. Standard Operating Conditions 50.3. DC Characteristics 50.3.1. Supply Voltage 50.3.2. Supply Current (IDD)(1,2,4) 50.3.3. Power-Down Current (IPD)(1,2) 50.3.4. I/O Ports 50.3.5. Memory Programming Specifications 50.3.6. Thermal Characteristics 50.4. AC Characteristics 50.4.1. External Clock/Oscillator Timing Requirements 50.4.2. Internal Oscillator Parameters(1) 50.4.3. PLL Specifications 50.4.4. I/O and CLKOUT Timing Specifications 50.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 50.4.6. High/Low-Voltage Detect Characteristics 50.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 50.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 50.4.9. Comparator Specifications 50.4.10. 8-Bit DAC Specifications 50.4.11. Fixed Voltage Reference (FVR) Specifications 50.4.12. Zero-Cross Detect (ZCD) Specifications 50.4.13. Timer0 and Timer1 External Clock Requirements 50.4.14. Capture/Compare/PWM Requirements (CCP) 50.4.15. SPI Mode Requirements 50.4.16. I2C Bus Start/Stop Bits Requirements 50.4.17. I2C Bus Data Requirements 50.4.18. Configurable Logic Cell (CLC) Characteristics 50.4.19. Temperature Indicator Requirements 51. DC and AC Characteristics Graphs and Tables 52. Packaging Information 52.1. Package Details 53. Appendix A: Revision History The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
The PIC18-Q84 microcontroller family is available in 28/40/44/48-pin devices for many automotive and industrial applications. The many communication peripherals found on the product family, such as CAN, SPI, I2C, two UARTs, can handle a wide range of wired and wireless (using external modules) communication protocols for intelligent applications. Combined with the Core Independent Peripherals integration capabilities, this capacity enables functions for motor control, power supply, sensor, signal and user interface applications. Additionally, this family includes a 12-bit ADC with Computation and Context Switching extensions for automated signal analysis to reduce the complexity of the application.
PIC18-Q84 Family Types Table 1. Devices Included in This Data Sheet T/ imer imer imer aveform imers 2 C oltage Detect atchdog T Device CCP (bytes) (bytes) (bytes) I/O Pins/ imer with HL CAN FD SPI/I UART/ Data SRAM Generator Oscillator 8-Bit DAC Data EEPROM 16-Bit T Comparator/ 16-Bit Dual PWM/ Zero-Cross Detect ectored Interrupts AG Boundary Scan Peripheral Pin Select 8-Bit T V Program Memory Flash 16-Bit Universal T Numerically Controlled Temperature Indicator JT Memory Access Partition/ Device Information Area Configurable Logic Cell indowed W Complimentary W Signal Measurement T High-Low V 32-Bit CRC with Scanner UART with Protocol Support Peripheral Module Disable Direct Memory Access (DMA) W 12-Bit ADC w/Computation and Context Switching (channels)
PIC18F26Q84 128k 12800 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y PIC18F46Q84 128k 12800 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y PIC18F56Q84 128k 12800 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 43 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Y
Features
• C Compiler Optimized RISC Architecture • Operating Speed: – DC – 64 MHz clock input – 62.5 ns minimum instruction cycle • Eight Direct Memory Access (DMA) Controllers: – Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces © 2020 Microchip Technology Inc.
Preliminary Datasheet
DS40002259A-page 1 Document Outline Introduction PIC18-Q84 Family Types Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Table of Contents 1. Packages 2. Pin Diagrams 3. Pin Allocation Tables 4. Guidelines for Getting Started with PIC18-Q84 Microcontrollers 4.1. Basic Connection Requirements 4.2. Power Supply Pins 4.2.1. Decoupling Capacitors 4.2.2. Tank Capacitors 4.3. Master Clear (MCLR) Pin 4.4. In-Circuit Serial Programming™ (ICSP™) Pins 4.5. External Oscillator Pins 4.6. Unused I/Os 5. Register and Bit Naming Conventions 5.1. Register Names 5.2. Bit Names 5.2.1. Short Bit Names 5.2.2. Long Bit Names 5.2.3. Bit Fields 5.3. Register and Bit Naming Exceptions 5.3.1. Status, Interrupt, and Mirror Bits 6. Register Legend 7. PIC18 CPU 7.1. System Arbitration 7.1.1. Priority Lock 7.2. Memory Access Scheme 7.2.1. ISR Priority > Main Priority > Peripheral Priority 7.2.2. Peripheral Priority > ISR Priority > Main Priority 7.2.3. ISR Priority > Peripheral Priority > Main Priority 7.2.4. Peripheral 1 Priority > ISR Priority > Main Priority > Peripheral 2 Priority 7.3. 8x8 Hardware Multiplier 7.3.1. Operation 7.3.2. 16x16 Unsigned Multiplication Algorithm 7.3.3. 16x16 Signed Multiplication Algorithm 7.4. PIC18 Instruction Cycle 7.4.1. Instruction Flow/Pipelining 7.4.2. Instructions in Program Memory 7.4.3. Multi-Word Instructions 7.5. STATUS Register 7.6. Call Shadow Register 7.7. Register Definitions: System Arbiter 7.7.1. ISRPR 7.7.2. MAINPR 7.7.3. DMAxPR 7.7.4. SCANPR 7.7.5. PRLOCK 7.7.6. PROD 7.7.7. STATUS 7.8. Register Summary - System Arbiter Control 8. Device Configuration 8.1. Configuration Settings 8.2. Code Protection 8.3. User ID 8.4. Device ID and Revision ID 8.5. Register Definitions: Configuration Words 8.5.1. CONFIG1 8.5.2. CONFIG2 8.5.3. CONFIG3 8.5.4. CONFIG4 8.5.5. CONFIG5 8.5.6. CONFIG6 8.5.7. CONFIG7 8.5.8. CONFIG8 8.5.9. CONFIG9 8.5.10. CONFIG10 8.5.11. CONFIG11 8.5.12. CRC Boot Polynomial 8.5.13. CRC Boot Seed 8.5.14. CRC Boot Expected Value 8.5.15. CRC Polynomial 8.5.16. CRC Seed 8.5.17. CRC Expected Value 8.6. Register Summary - Configuration Settings 8.7. Register Definitions: Device ID and Revision ID 8.7.1. Device ID 8.7.2. Revision ID 8.8. Register Summary - DEVID/REVID 9. Memory Organization 9.1. Program Memory Organization 9.1.1. Memory Access Partition 9.1.1.1. Application Block 9.1.1.2. Boot Block 9.1.1.3. Storage Area Flash 9.1.2. Program Counter 9.1.3. Return Address Stack 9.1.3.1. Top-of-Stack Access 9.1.3.2. Return Stack Pointer 9.1.3.3. PUSH and POP Instructions 9.1.3.4. Fast Register Stack 9.1.4. Look-up Tables in Program Memory 9.1.4.1. Computed GOTO 9.1.4.2. Program Flash Memory Access 9.2. Device Information Area 9.2.1. Microchip Unique Identifier (MUI) 9.2.2. External Unique Identifier (EUI) 9.2.3. Standard Parameters for the Temperature Sensor 9.2.4. Fixed Voltage Reference Data 9.3. Device Configuration Information 9.4. Data Memory Organization 9.4.1. Bank Select Register 9.4.2. Access Bank 9.5. Data Addressing Modes 9.5.1. Inherent and Literal Addressing 9.5.2. Direct Addressing 9.5.3. Indirect Addressing 9.5.3.1. FSR Registers and the INDF Operand 9.5.3.2. FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 9.5.3.3. Operations by FSRs on FSRs 9.6. Data Memory and the Extended Instruction Set 9.6.1. Indexed Addressing with Literal Offset 9.6.2. Instructions Affected by Indexed Literal Offset Mode 9.6.3. Mapping the Access Bank in Indexed Literal Offset Mode 9.6.4. PIC18 Instruction Execution and the Extended Instruction Set 9.7. Register Definitions: Memory Organization 9.7.1. PCL 9.7.2. PCLAT 9.7.3. TOS 9.7.4. STKPTR 9.7.5. WREG 9.7.6. INDF 9.7.7. POSTDEC 9.7.8. POSTINC 9.7.9. PREINC 9.7.10. PLUSW 9.7.11. FSR 9.7.12. BSR 9.8. Register Summary - Memory Organization 10. NVM - Nonvolatile Memory Module 10.1. Operations 10.2. Unlock Sequence 10.3. Program Flash Memory (PFM) 10.3.1. Page Erase 10.3.2. Page Read 10.3.3. Word Read 10.3.4. Page Write 10.3.5. Word Write 10.3.6. Word Modify 10.3.7. Write Verify 10.3.8. Unexpected Termination of Write Operation 10.3.9. User ID, Device ID, Configuration Settings Access, DIA and DCI 10.3.10. Table Pointer Operations 10.3.10.1. Table Pointer Register 10.3.10.2. Table Latch Register 10.3.10.3. Table Read Operations 10.3.10.4. Table Write Operations 10.3.10.5. Table Pointer Boundaries 10.3.10.6. Reading the Program Flash Memory 10.4. Data Flash Memory (DFM) 10.4.1. Reading the DFM 10.4.2. Writing to DFM 10.4.3. Erasing the DFM 10.4.4. DFM Write Verify 10.4.5. Operation During Code-Protect and Write-Protect 10.4.6. Protection Against Spurious Writes 10.5. Register Definitions: NVM 10.5.1. NVMCON0 10.5.2. NVMCON1 10.5.3. NVMLOCK 10.5.4. NVMADR 10.5.5. NVMDAT 10.5.6. TBLPTR 10.5.7. TABLAT 10.6. Register Summary - NVM 11. VIC - Vectored Interrupt Controller Module 11.1. Overview 11.2. Interrupt Control and Status Registers 11.3. Interrupt Vector Table 11.3.1. Interrupt Vector Table Base Address (IVTBASE) 11.3.2. Interrupt Vector Table Contents 11.3.3. Interrupt Vector Table Address Calculation 11.3.4. Access Control for IVTBASE Registers 11.4. Interrupt Priority 11.4.1. User (Software) Priority 11.4.2. Natural Order (Hardware) Priority 11.5. Interrupt Operation 11.5.1. Serving a High- or Low-Priority Interrupt while the Main Routine Code is Executing 11.5.2. Serving a High-Priority Interrupt while a Low-Priority Interrupt is Pending 11.5.3. Preempting Low-Priority Interrupts 11.5.4. Simultaneous High- and Low-Priority Interrupts 11.6. Context Saving 11.6.1. Accessing Shadow Registers 11.7. Returning from Interrupt Service Routine (ISR) 11.8. Interrupt Latency 11.8.1. Aborting Interrupts 11.9. Interrupt Setup Procedure 11.10. External Interrupt Pins 11.11. Wake-up from Sleep 11.12. Interrupt Compatibility 11.13. Register Definitions: Interrupt Control 11.13.1. INTCON0 11.13.2. INTCON1 11.13.3. IVTBASE 11.13.4. IVTAD 11.13.5. IVTLOCK 11.13.6. SHADCON 11.13.7. PIE0 11.13.8. PIE1 11.13.9. PIE2 11.13.10. PIE3 11.13.11. PIE4 11.13.12. PIE5 11.13.13. PIE6 11.13.14. PIE7 11.13.15. PIE8 11.13.16. PIE9 11.13.17. PIE10 11.13.18. PIE11 11.13.19. PIE12 11.13.20. PIE13 11.13.21. PIE14 11.13.22. PIE15 11.13.23. PIR0 11.13.24. PIR1 11.13.25. PIR2 11.13.26. PIR3 11.13.27. PIR4 11.13.28. PIR5 11.13.29. PIR6 11.13.30. PIR7 11.13.31. PIR8 11.13.32. PIR9 11.13.33. PIR10 11.13.34. PIR11 11.13.35. PIR12 11.13.36. PIR13 11.13.37. PIR14 11.13.38. PIR15 11.13.39. IPR0 11.13.40. IPR1 11.13.41. IPR2 11.13.42. IPR3 11.13.43. IPR4 11.13.44. IPR5 11.13.45. IPR6 11.13.46. IPR7 11.13.47. IPR8 11.13.48. IPR9 11.13.49. IPR10 11.13.50. IPR11 11.13.51. IPR12 11.13.52. IPR13 11.13.53. IPR14 11.13.54. IPR15 11.14. Register Summary - Interrupts 12. OSC - Oscillator Module (With Fail-Safe Clock Monitor) 12.1. Clock Source Types 12.1.1. External Clock Sources 12.1.1.1. EC Mode 12.1.1.2. LP, XT, HS Modes 12.1.1.3. Oscillator Start-Up Timer (OST) 12.1.1.4. 4x PLL 12.1.1.5. Secondary Oscillator 12.1.1.5.1. SOSC Start-Up Timing 12.1.2. Internal Clock Sources 12.1.2.1. HFINTOSC 12.1.2.1.1. HFINTOSC Frequency Tuning 12.1.2.2. MFINTOSC 12.1.2.3. LFINTOSC 12.1.2.4. ADCRC 12.1.3. Oscillator Status and Manual Enable 12.2. Clock Switching 12.2.1. NOSC and NDIV Bits 12.2.2. COSC and CDIV Bits 12.2.3. CSWHOLD 12.2.4. PLL Input Switch 12.2.5. Clock Switch and Sleep 12.3. Fail-Safe Clock Monitor (FSCM) 12.3.1. Fail-Safe Detection 12.3.2. Fail-Safe Operation - FOSC Fail-Safe Clock Monitor 12.3.3. Fail-Safe Operation - Primary and Secondary Fail-Safe Clock Monitors 12.3.4. Fail-Safe Clock Monitor Fault Injection 12.3.5. Fail-Safe Condition Clearing 12.3.6. Reset or Wake-Up From Sleep 12.4. Active Clock Tuning (ACT) 12.4.1. ACT Lock Status 12.4.2. ACT Out-Of-Range Status 12.4.3. ACT Update Disable 12.4.4. ACT Interrupts 12.5. Register Definitions: Oscillator Module 12.5.1. ACTCON 12.5.2. OSCCON1 12.5.3. OSCCON2 12.5.4. OSCCON3 12.5.5. OSCTUNE 12.5.6. OSCFRQ 12.5.7. OSCSTAT 12.5.8. OSCEN 12.5.9. FSCMCON 12.6. Register Summary - Oscillator Module 13. CRC - Cyclic Redundancy Check Module with Memory Scanner 13.1. Module Overview 13.2. Polynomial Implementation 13.3. Data Sources 13.3.1. CRC from User Data 13.3.2. CRC from Flash 13.4. CRC Check Value 13.5. CRC Interrupt 13.6. Configuring the CRC Module 13.6.1. Register Overlay 13.7. Scanner Module Overview 13.8. Scanning Modes 13.8.1. TRIGEN = 0, BURSTMD = 0 13.8.2. TRIGEN = 1, BURSTMD = 0 13.8.3. TRIGEN = x, BURSTMD = 1 13.8.4. WWDT Interaction 13.9. Configuring the Scanner 13.10. Scanner Interrupt 13.11. Peripheral Module Disable 13.12. CRC-on-Boot Module Overview 13.12.1. Enabling the Module 13.12.2. Polynomial, Seed, and Expected Values 13.12.3. Memory Selection 13.12.4. Output Pin Setup 13.12.5. CRC Calculation 13.12.6. Mismatch Condition 13.13. Register Definitions: CRC and Scanner Control 13.13.1. CRCCON0 13.13.2. CRCCON1 13.13.3. CRCCON2 13.13.4. CRCDATA 13.13.5. CRCOUT 13.13.6. CRCSHIFT 13.13.7. CRCXOR 13.13.8. SCANCON0 13.13.9. SCANLADR 13.13.10. SCANHADR 13.13.11. SCANTRIG 13.13.12. BOOTREG 13.14. Register Summary - CRC 14. Resets 14.1. Power-on Reset (POR) 14.2. Brown-out Reset (BOR) 14.2.1. BOR is Always ON 14.2.2. BOR is OFF in Sleep 14.2.3. BOR Controlled by Software 14.2.4. BOR is always OFF 14.2.5. BOR and Bulk Erase 14.3. Low-Power Brown-out Reset (LPBOR) 14.3.1. Enabling LPBOR 14.3.2. LPBOR Module Output 14.4. MCLR Reset 14.4.1. MCLR Enabled 14.4.2. MCLR Disabled 14.5. Windowed Watchdog Timer (WWDT) Reset 14.6. RESET Instruction 14.7. Stack Overflow/Underflow Reset 14.8. Programming Mode Exit 14.9. Power-up Timer (PWRT) 14.10. Start-up Sequence 14.10.1. Memory Execution Violation 14.11. Determining the Cause of a Reset 14.12. Power Control (PCON0/PCON1) Registers 14.13. Register Definitions: Power Control 14.13.1. BORCON 14.13.2. PCON0 14.13.3. PCON1 14.14. Register Summary - BOR Control and Power Control 15. WWDT - Windowed Watchdog Timer 15.1. Independent Clock Source 15.2. WWDT Operating Modes 15.2.1. WWDT Is Always On 15.2.2. WWDT is Off in Sleep 15.2.3. WWDT Controlled by Software 15.3. Time-out Period 15.4. Watchdog Window 15.5. Clearing the Watchdog Timer 15.5.1. CLRWDT Considerations (Windowed Mode) 15.6. Operation During Sleep 15.7. Register Definitions: Windowed Watchdog Timer Control 15.7.1. WDTCON0 15.7.2. WDTCON1 15.7.3. WDTPSH 15.7.4. WDTPSL 15.7.5. WDTTMR 15.8. Register Summary: WDT Control 16. DMA - Direct Memory Access 16.1. DMA Registers 16.2. DMA Organization 16.3. DMA Interface 16.3.1. Special Function Registers with DMA Access only 16.3.2. DMA Addressing 16.3.3. DMA Message Size/Counters 16.3.4. DMA Message Transfers 16.3.4.1. Starting DMA Message Transfers 16.3.4.1.1. User Software Control 16.3.4.1.2. Hardware Trigger, SIRQ 16.3.4.2. Stopping DMA Message Transfers 16.3.4.2.1. User Software Control 16.3.4.2.2. Hardware Trigger, AIRQ 16.3.4.2.3. Source Count Reload 16.3.4.2.4. Destination Count Reload 16.3.4.2.5. Clearing the EN bit 16.4. Disable DMA Message Transfer Upon Completion 16.4.1. Clearing the SIRQEN bit 16.4.2. Source/Destination Stop 16.5. Types of Hardware Triggers 16.5.1. Edge Trigger Requests 16.5.2. Level Trigger Requests 16.6. Types of Data Transfers 16.7. DMA Interrupts 16.7.1. DMA Source Count Interrupt 16.7.2. DMA Destination Count Interrupt 16.7.3. Abort Interrupt 16.7.4. Overrun Interrupt 16.8. DMA Setup and Operation 16.8.1. Source Stop 16.8.2. Destination Stop 16.8.3. Continuous Transfer 16.8.4. Transfer from SFR to GPR 16.8.5. Overrun Condition 16.8.6. Abort Trigger, Message Complete 16.8.7. Abort Trigger, Message in Progress 16.9. Reset 16.10. Power-Saving Mode Operation 16.10.1. Sleep Mode 16.10.2. Idle Mode 16.10.3. Doze Mode 16.10.4. Peripheral Module Disable 16.11. Example Setup Code 16.12. Register Overlay 16.13. Register Definitions: DMA 16.13.1. DMASELECT 16.13.2. DMAnCON0 16.13.3. DMAnCON1 16.13.4. DMAnBUF 16.13.5. DMAnSSA 16.13.6. DMAnSSZ 16.13.7. DMAnSCNT 16.13.8. DMAnSPTR 16.13.9. DMAnDSA 16.13.10. DMAnDSZ 16.13.11. DMAnDCNT 16.13.12. DMAnDPTR 16.13.13. DMAnSIRQ 16.13.14. DMAnAIRQ 16.14. Register Summary - DMA 17. Power-Saving Modes 17.1. Doze Mode 17.1.1. Doze Operation 17.1.2. Interrupts During Doze 17.2. Sleep Mode 17.2.1. Wake-up from Sleep 17.2.2. Wake-up Using Interrupts 17.2.3. Low-Power Sleep Mode 17.2.3.1. Sleep Current vs. Wake-up Time 17.2.3.2. Peripheral Usage in Sleep 17.3. Idle Mode 17.3.1. Idle and Interrupts 17.3.2. Idle and WWDT 17.4. Peripheral Operation in Power-Saving Modes 17.5. Register Definitions: Power-Savings Control 17.5.1. CPUDOZE 17.5.2. VREGCON 17.6. Register Summary - Power-Savings Control 18. PMD - Peripheral Module Disable 18.1. Overview 18.2. Disabling a Module 18.3. Enabling a Module 18.4. Register Definitions: Peripheral Module Disable 18.4.1. PMD0 18.4.2. PMD1 18.4.3. PMD2 18.4.4. PMD3 18.4.5. PMD4 18.4.6. PMD5 18.4.7. PMD6 18.4.8. PMD7 18.4.9. PMD8 18.5. Register Summary - PMD 19. I/O Ports 19.1. Overview 19.2. PORTx - Data Register 19.3. LATx - Output Latch 19.4. TRISx - Direction Control 19.5. ANSELx - Analog Control 19.6. WPUx - Weak Pull-Up Control 19.7. INLVLx - Input Threshold Control 19.8. SLRCONx - Slew Rate Control 19.9. ODCONx - Open-Drain Control 19.10. Edge Selectable Interrupt-on-Change 19.11. I2C Pad Control 19.12. I/O Priorities 19.13. MCLR/VPP/RE3 Pin 19.14. Register Definitions: Port Control 19.14.1. PORTx 19.14.2. LATx 19.14.3. TRISx 19.14.4. ANSELx 19.14.5. WPUx 19.14.6. INLVLx 19.14.7. SLRCONx 19.14.8. ODCONx 19.14.9. RxyI2C 19.15. Register Summary - IO Ports 20. IOC - Interrupt-on-Change 20.1. Overview 20.2. Enabling the Module 20.3. Individual Pin Configuration 20.4. Interrupt Flags 20.5. Clearing Interrupt Flags 20.6. Operation in Sleep 20.7. Register Definitions: Interrupt-on-Change Control 20.7.1. IOCxF 20.7.2. IOCxN 20.7.3. IOCxP 20.8. Register Summary: Interrupt-on-Change Control 21. PPS - Peripheral Pin Select Module 21.1. Overview 21.2. PPS Inputs 21.3. PPS Outputs 21.4. Bidirectional Pins 21.5. PPS Lock 21.5.1. PPS One-Way Lock 21.6. Operation During Sleep 21.7. Effects of a Reset 21.8. Register Definitions: Peripheral Pin Select (PPS) 21.8.1. xxxPPS 21.8.2. RxyPPS 21.8.3. PPSLOCK 21.9. Register Summary: Peripheral Pin Select Module 21.9.1. CANRXPPS 22. CLC - Configurable Logic Cell 22.1. CLC Setup 22.1.1. Data Selection 22.1.2. Data Gating 22.1.3. Logic Function 22.1.4. Output Polarity 22.2. CLC Interrupts 22.3. Effects of a Reset 22.4. Output Mirror Copies 22.5. Operation During Sleep 22.6. CLC Setup Steps 22.7. Register Overlay 22.8. Register Definitions: Configurable Logic Cell 22.8.1. CLCSELECT 22.8.2. CLCnCON 22.8.3. CLCnPOL 22.8.4. CLCnSEL0 22.8.5. CLCnSEL1 22.8.6. CLCnSEL2 22.8.7. CLCnSEL3 22.8.8. CLCnGLS0 22.8.9. CLCnGLS1 22.8.10. CLCnGLS2 22.8.11. CLCnGLS3 22.8.12. CLCDATA 22.9. Register Summary - CLC Control 23. CLKREF - Reference Clock Output Module 23.1. Clock Source 23.1.1. Clock Synchronization 23.2. Programmable Clock Divider 23.3. Selectable Duty Cycle 23.4. Operation in Sleep Mode 23.5. Register Definitions: Reference Clock 23.5.1. CLKRCON 23.5.2. CLKRCLK 23.6. Register Summary: Reference CLK 24. TMR0 - Timer0 Module 24.1. Timer0 Operation 24.1.1. 8-Bit Mode 24.1.2. 16-Bit Mode 24.2. Clock Selection 24.2.1. Synchronous Mode 24.2.2. Asynchronous Mode 24.2.3. Programmable Prescaler 24.2.4. Programmable Postscaler 24.3. Timer0 Output and Interrupt 24.3.1. Timer0 Output 24.3.2. Timer0 Interrupt 24.3.3. Timer0 Example 24.4. Operation During Sleep 24.5. Register Definitions: Timer0 Control 24.5.1. T0CON0 24.5.2. T0CON1 24.5.3. TMR0H 24.5.4. TMR0L 24.6. Register Summary: Timer0 25. TMR1 - Timer1 Module with Gate Control 25.1. Timer1 Operation 25.2. Clock Source Selection 25.2.1. Internal Clock Source 25.2.2. External Clock Source 25.3. Timer1 Prescaler 25.4. Secondary Oscillator 25.5. Timer1 Operation in Asynchronous Counter Mode 25.5.1. Reading and Writing TMRx in Asynchronous Counter Mode 25.6. Timer1 16-Bit Read/Write Mode 25.7. Timer1 Gate 25.7.1. Timer1 Gate Enable 25.7.2. Timer1 Gate Source Selection 25.7.3. Timer1 Gate Toggle Mode 25.7.4. Timer1 Gate Single Pulse Mode 25.7.5. Timer1 Gate Value Status 25.7.6. Timer1 Gate Event Interrupt 25.8. Timer1 Interrupt 25.9. Timer1 Operation During Sleep 25.10. CCP Capture/Compare Time Base 25.11. CCP Special Event Trigger 25.12. Peripheral Module Disable 25.13. Register Definitions: Timer1 Control 25.13.1. TxCON 25.13.2. TxGCON 25.13.3. TxCLK 25.13.4. TxGATE 25.13.5. TMRx 25.14. Register Summary Timer 1 26. TMR2 - Timer2 Module 26.1. Timer2 Operation 26.1.1. Free-Running Period Mode 26.1.2. One-Shot Mode 26.1.3. Monostable Mode 26.2. Timer2 Output 26.3. External Reset Sources 26.4. Timer2 Interrupt 26.5. PSYNC bit 26.6. CSYNC bit 26.7. Operating Modes 26.8. Operation Examples 26.8.1. Software Gate Mode 26.8.2. Hardware Gate Mode 26.8.3. Edge-Triggered Hardware Limit Mode 26.8.4. Level-Triggered Hardware Limit Mode 26.8.5. Software Start One-Shot Mode 26.8.6. Edge-Triggered One-Shot Mode 26.8.7. Edge-Triggered Hardware Limit One-Shot Mode 26.8.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 26.8.9. Edge-Triggered Monostable Modes 26.8.10. Level-Triggered Hardware Limit One-Shot Modes 26.9. Timer2 Operation During Sleep 26.10. Register Definitions: Timer2 Control 26.10.1. TxTMR 26.10.2. TxPR 26.10.3. TxCON 26.10.4. TxHLT 26.10.5. TxCLKCON 26.10.6. TxRST 26.11. Register Summary - Timer2 27. SMT - Signal Measurement Timer 27.1. SMT Operation 27.1.1. Clock Source Selection 27.1.2. Signal and Window Source Selection 27.1.3. Time Base 27.1.4. Pulse Width and Period Captures 27.1.5. Status Information 27.1.6. Modes of Operation 27.1.6.1. Timer Mode 27.1.6.2. Gated Timer Mode 27.1.6.3. Period and Duty Cycle Measurement Mode 27.1.6.4. High and Low Measurement Mode 27.1.6.5. Windowed Measurement Mode 27.1.6.6. Gated Window Measurement Mode 27.1.6.7. Time-of-Flight Measurement Mode 27.1.6.8. Capture Mode 27.1.6.9. Counter Mode 27.1.6.10. Gated Counter Mode 27.1.6.11. Windowed Counter Mode 27.1.7. Interrupts 27.1.8. Operation During Sleep 27.2. Register Definitions: SMT Control 27.2.1. SMTxCON0 27.2.2. SMTxCON1 27.2.3. SMTxSTAT 27.2.4. SMTxCLK 27.2.5. SMTxWIN 27.2.6. SMTxSIG 27.2.7. SMTxTMR 27.2.8. SMTxCPR 27.2.9. SMTxCPW 27.2.10. SMTxPR 27.3. Register Summary - SMT Control 28. UTMR - Universal Timer Module 28.1. Module Nomenclature 28.2. Clock Source Selection 28.3. UTMR Prescaler 28.4. UTMR Operation 28.4.1. Synchronous vs. Asynchronous Operation 28.4.2. Timer Counter and Capture Registers 28.4.3. Timer Period Register 28.4.4. External Reset Source (ERS) 28.4.5. Start, Stop and Reset Events 28.4.5.1. Start Event 28.4.5.2. Reset Event 28.4.5.3. Stop Event 28.4.6. Hardware Limit Mode 28.4.7. One-Shot Mode 28.4.8. Run Status Flag 28.5. UTMR Output Modes 28.6. Interrupt and DMA Triggers 28.7. Operation During Sleep 28.8. Chaining Counter Timers 28.9. Register Definitions: Universal Timer 28.9.1. TUxyCON0 28.9.2. TUxyCON1 28.9.3. TUxyHLT 28.9.4. TUxyPS 28.9.5. TUxyTMR (16-bit) 28.9.6. TUxyCR (16-bit) 28.9.7. TUxyPR (16-bit) 28.9.8. TUxyCLK 28.9.9. TUxyERS 28.9.10. TUCHAIN 28.10. Register Summary - Universal Timer 29. CCP - Capture/Compare/PWM Module 29.1. CCP Module Configuration 29.1.1. CCP Modules and Timer Resources 29.1.2. Open-Drain Output Option 29.2. Capture Mode 29.2.1. Capture Sources 29.2.2. Timer1 Mode for Capture 29.2.3. Software Interrupt Mode 29.2.4. CCP Prescaler 29.2.5. Capture During Sleep 29.3. Compare Mode 29.3.1. CCPx Pin Configuration 29.3.2. Timer1 Mode for Compare 29.3.3. Compare During Sleep 29.4. PWM Overview 29.4.1. Standard PWM Operation 29.4.2. Setup for PWM Operation 29.4.3. Timer2 Timer Resource 29.4.4. PWM Period 29.4.5. PWM Duty Cycle 29.4.6. PWM Resolution 29.4.7. Operation in Sleep Mode 29.4.8. Changes in System Clock Frequency 29.4.9. Effects of Reset 29.5. Register Definitions: CCP Control 29.5.1. CCPxCON 29.5.2. CCPxCAP 29.5.3. CCPRx 29.6. Register Summary - CCP Control 30. Capture, Compare, and PWM Timers Selection 30.1. Register Definitions: Capture, Compare, and PWM Timer Selection 30.1.1. CCPTMRS0 30.2. Register Summary - Capture, Compare, and PWM Timers Selection 31. PWM - Pulse-Width Modulator with Compare 31.1. Output Slices 31.1.1. Output Polarity 31.1.2. Operating Modes 31.1.2.1. Left Aligned Mode 31.1.2.2. Right Aligned Mode 31.1.2.3. Center Aligned Mode 31.1.2.4. Variable Alignment Mode 31.1.2.5. Compare Modes 31.1.2.5.1. Pulsed Compare Mode 31.1.2.5.2. Toggled Compare 31.1.3. Push-Pull Mode 31.2. Period Timer 31.3. Clock Sources 31.3.1. Clock Prescaler 31.4. External Period Resets 31.5. Buffered Period and Parameter Registers 31.6. Synchronizing Multiple PWMs 31.7. Interrupts 31.7.1. Period Interrupt 31.7.1.1. Period Interrupt Postscaler 31.7.2. Parameter Interrupts 31.8. Operation During Sleep 31.9. Register Definitions: PWM Control 31.9.1. PWMxERS 31.9.2. PWMxCLK 31.9.3. PWMxLDS 31.9.4. PWMxPR 31.9.5. PWMxCPRE 31.9.6. PWMxPIPOS 31.9.7. PWMxGIR 31.9.8. PWMxGIE 31.9.9. PWMxCON 31.9.10. PWMxSaCFG 31.9.11. PWMxSaP1 31.9.12. PWMxSaP2 31.9.13. PWMLOAD 31.9.14. PWMEN 31.10. Register Summary - PWM 32. CWG - Complementary Waveform Generator Module 32.1. Fundamental Operation 32.2. Operating Modes 32.2.1. Half-Bridge Mode 32.2.2. Push-Pull Mode 32.2.3. Full-Bridge Mode 32.2.3.1. Direction Change in Full-Bridge Mode 32.2.3.2. Dead-Band Delay in Full-Bridge Mode 32.2.4. Steering Modes 32.2.4.1. Synchronous Steering Mode 32.2.4.2. Asynchronous Steering Mode 32.2.4.3. Start-up Considerations 32.3. Clock Source 32.4. Selectable Input Sources 32.5. Output Control 32.5.1. CWG Output 32.5.2. Polarity Control 32.6. Dead-Band Control 32.6.1. Dead-Band Functionality In Half-Bridge Mode 32.6.2. Dead-Band Functionality In Full-Bridge Mode 32.7. Rising Edge and Reverse Dead-Band 32.8. Falling Edge and Forward Dead Band 32.9. Dead-Band Jitter 32.10. Auto-Shutdown 32.10.1. Shutdown 32.10.2. Software Generated Shutdown 32.10.3. External Input Source 32.10.4. Pin Override Levels 32.10.5. Auto-Shutdown Interrupts 32.11. Auto-Shutdown Restart 32.11.1. Software-Controlled Restart 32.11.2. Auto-Restart 32.12. Operation During Sleep 32.13. Configuring the CWG 32.14. Register Definitions: CWG Control 32.14.1. CWGxCON0 32.14.2. CWGxCON1 32.14.3. CWGxCLK 32.14.4. CWGxISM 32.14.5. CWGxSTR 32.14.6. CWGxAS0 32.14.7. CWGxAS1 32.14.8. CWGxDBR 32.14.9. CWGxDBF 32.15. Register Summary - CWG 33. NCO - Numerically Controlled Oscillator Module 33.1. NCO Operation 33.1.1. NCO Clock Sources 33.1.2. Accumulator 33.1.3. Adder 33.1.4. Increment Registers 33.2. Fixed Duty Cycle Mode 33.3. Pulse Frequency Mode 33.4. Output Polarity Control 33.5. Interrupts 33.6. Effects of a Reset 33.7. Operation in Sleep 33.8. Register Definitions: NCO 33.8.1. NCOxCON 33.8.2. NCOxCLK 33.8.3. NCOxACC 33.8.4. NCOxINC 33.9. Register Summary - NCO 34. DSM - Data Signal Modulator Module 34.1. DSM Operation 34.1.1. Modulator Signal Sources 34.1.2. Carrier Signal Sources 34.2. Carrier Synchronization 34.3. Carrier Source Polarity Select 34.4. Programmable Modulator Data 34.5. Modulated Output Polarity 34.6. Operation in Sleep Mode 34.7. Effects of a Reset 34.8. Peripheral Module Disable 34.9. Register Definitions: Modulation Control 34.9.1. MDxCON0 34.9.2. MDxCON1 34.9.3. MDxCARH 34.9.4. MDxCARL 34.9.5. MDxSRC 34.10. Register Summary - DSM 35. UART - Universal Asynchronous Receiver Transmitter with Protocol Support 35.1. UART I/O Pin Configuration 35.2. UART Asynchronous Modes 35.2.1. UART Asynchronous Transmitter 35.2.1.1. Enabling the Transmitter 35.2.1.2. Transmitting Data 35.2.1.3. Transmit Data Polarity 35.2.1.4. Transmit Interrupt Flag 35.2.1.5. TSR Status 35.2.1.6. Transmitter 7-bit Mode 35.2.1.7. Transmitter Parity Modes 35.2.1.8. Asynchronous Transmission Setup 35.2.2. UART Asynchronous Receiver 35.2.2.1. Enabling the Receiver 35.2.2.2. Receiving Data 35.2.2.3. Receive Data Polarity 35.2.2.4. Receive Interrupts 35.2.2.5. Receive Framing Error 35.2.2.6. Receiver Parity Modes 35.2.2.7. Receive FIFO Overflow 35.2.2.8. Asynchronous Reception Setup 35.2.3. Asynchronous Address Mode 35.2.3.1. Address Mode Transmit 35.2.3.2. Address Mode Receive 35.3. DMX Mode (Full-featured UARTs only) 35.3.1. DMX Controller 35.3.2. DMX Receiver 35.4. LIN Modes (Full-featured UARTs only) 35.4.1. LIN Master/Slave Mode 35.4.2. LIN Slave Mode 35.4.2.1. LIN Slave Receiver 35.4.2.2. LIN Slave Transmitter 35.5. DALI Mode (Full-featured UARTs only) 35.5.1. Control Device 35.5.2. Control Gear 35.6. General Purpose Manchester (Full-featured UARTs only) 35.7. Polarity 35.8. Stop Bits 35.8.1. Delayed Receive Interrupt 35.9. Operation After FIFO Overflow 35.10. Receive and Transmit Buffers 35.10.1. FIFO Status 35.10.2. FIFO Reset 35.11. Flow Control 35.11.1. Hardware Flow Control 35.11.2. RS-485 Transceiver Control 35.11.3. XON/XOFF Flow Control 35.12. Checksum (Full-featured UARTs only) 35.12.1. Transmit Checksum Method 35.12.2. Receive Checksum Method 35.13. Collision Detection (Full-featured UARTs only) 35.14. RX/TX Activity Time-out 35.15. Clock Accuracy With Asynchronous Operation 35.16. UART Baud Rate Generator 35.16.1. Auto-Baud Detect 35.16.2. Auto-Baud Overflow 35.16.3. Auto Wake-on-Break 35.16.3.1. Auto Wake-Up Special Considerations 35.17. Transmitting a Break 35.18. Receiving a Break 35.19. UART Operation During Sleep 35.20. Register Definitions: UART 35.20.1. UxCON0 35.20.2. UxCON1 35.20.3. UxCON2 35.20.4. UxERRIR 35.20.5. UxERRIE 35.20.6. UxUIR 35.20.7. UxFIFO 35.20.8. UxBRG 35.20.9. UxRXB 35.20.10. UxTXB 35.20.11. UxP1 35.20.12. UxP2 35.20.13. UxP3 35.20.14. UxTXCHK 35.20.15. UxRXCHK 35.21. Register Summary - UART 36. SPI - Serial Peripheral Interface Module 36.1. SPI Controls 36.2. SPI Operation 36.2.1. Enabling and Disabling the SPI Module 36.2.2. BUSY Bit 36.2.3. Transmit and Receive FIFOs 36.2.4. LSb vs. MSb-First Operation 36.2.5. Input and Output Polarity Control 36.2.6. Transfer Counter 36.2.6.1. Total Bit Count Mode (BMODE = 0) 36.2.6.2. Variable Transfer Size Mode (BMODE = 1) 36.2.6.3. Transfer Counter in Slave Mode 36.3. Master Mode 36.3.1. Full-Duplex Mode 36.3.2. Transmit Only Mode 36.3.3. Receive Only Mode 36.3.4. Transfer Off Mode 36.3.5. Master Mode Slave Select Control 36.3.5.1. Hardware Slave Select Control 36.3.5.2. Software Slave Select Control 36.3.6. Master Mode SPI Clock Configuration 36.3.6.1. SPI Clock Selection 36.3.6.2. Clock and Data Change Alignment 36.3.6.3. SCK Start-up Delay 36.4. Slave Mode 36.4.1. Slave Mode Transmit Options 36.4.1.1. SDO Drive/Tri-state 36.4.1.2. SDO Output Data 36.4.2. Slave Mode Receive Options 36.4.3. Slave Mode Slave Select 36.4.4. Slave Mode Clock Configuration 36.4.5. Daisy-Chain Configuration 36.5. SPI Operation In Sleep Mode 36.6. SPI Interrupts 36.6.1. SPI Receive Interrupt 36.6.2. SPI Transmit Interrupt 36.6.3. SPI Status Interrupts 36.6.3.1. Shift Register Empty Interrupt 36.6.3.2. Transfer Counter is Zero Interrupt 36.6.3.3. Start of Slave Select and End of Slave Select Interrupts 36.6.3.4. Receiver Overflow and Transmitter Underflow Interrupts 36.7. Register Definitions: Serial Peripheral Interface 36.7.1. SPIxCON0 36.7.2. SPIxCON1 36.7.3. SPIxCON2 36.7.4. SPIxCLK 36.7.5. SPIxBAUD 36.7.6. SPIxTCNT 36.7.7. SPIxTWIDTH 36.7.8. SPIxSTATUS 36.7.9. SPIxRXB 36.7.10. SPIxTXB 36.7.11. SPIxINTE 36.7.12. SPIxINTF 36.8. Register Summary - SPI Control 37. I2C - Inter-Integrated Circuit Module 37.1. I2C Features 37.2. I2C Terminology 37.3. I2C Module Overview 37.3.1. Byte Format 37.3.2. SDA and SCL Pins 37.3.2.1. SDA Hold Time 37.3.3. Start Condition 37.3.4. Acknowledge Sequence 37.3.5. Restart Condition 37.3.6. Stop Condition 37.3.7. Bus Timeout 37.3.8. Address Buffers 37.3.9. Transmit Buffer 37.3.10. Receive Buffer 37.3.11. Clock Stretching 37.3.11.1. Clock Stretching for Buffer Operations 37.3.11.2. Clock Stretching for Other Slave Operations 37.3.12. Data Byte Count 37.3.12.1. Auto-Load I2CxCNT 37.3.13. DMA Integration 37.3.13.1. 7-Bit Master Transmission 37.3.13.2. 10-Bit Master Transmission 37.3.13.3. 7/10-Bit Master Reception 37.3.13.4. 7-Bit Slave Transmission 37.3.13.5. 10-Bit Slave Transmission 37.3.13.6. 7/10-Bit Slave Reception 37.3.14. Interrupts 37.3.14.1. High-Level Interrupts 37.3.14.2. Condition-Specific Interrupts 37.3.15. Operation in Sleep 37.4. I2C Operation 37.4.1. I2C Slave Mode Operation 37.4.1.1. Slave Addressing Modes 37.4.1.2. General Call Addressing Support 37.4.1.3. Slave Operation in 7-Bit Addressing Modes 37.4.1.3.1. Slave Transmission (7-bit Addressing Mode) 37.4.1.3.2. Slave Reception (7-Bit Addressing Mode) 37.4.1.4. Slave Operation in 10-Bit Addressing Modes 37.4.1.4.1. Slave Transmission (10-Bit Addressing Mode) 37.4.1.4.2. Slave Reception (10-Bit Addressing Mode) 37.4.2. I2C Master Mode Operation 37.4.2.1. Bus Free Time 37.4.2.2. Master Clock Timing 37.4.2.3. Start Condition Timing 37.4.2.4. Acknowledge Sequence Timing 37.4.2.5. Restart Condition Timing 37.4.2.6. Stop Condition Timing 37.4.2.7. Master Operation in 7-Bit Addressing Modes 37.4.2.7.1. Master Transmission (7-Bit Addressing Mode) 37.4.2.7.2. Master Reception (7-Bit Addressing Mode) 37.4.2.8. Master Operation in 10-Bit Addressing Modes 37.4.2.8.1. Master Transmission (10-Bit) 37.4.2.8.2. Master Reception (10-Bit Addressing Mode) 37.4.3. I2C Multi-Master Mode Operation 37.4.3.1. Multi-Master Mode Clock Synchronization 37.4.3.2. Multi-Master Mode Bus Arbitration 37.5. Register Definitions: I2C Control 37.5.1. I2CxCON0 37.5.2. I2CxCON1 37.5.3. I2CxCON2 37.5.4. I2CxSTAT0 37.5.5. I2CxSTAT1 37.5.6. I2CxPIR 37.5.7. I2CxPIE 37.5.8. I2CxERR 37.5.9. I2CxCLK 37.5.10. I2CxBAUD 37.5.11. I2CxCNT 37.5.12. I2CxBTO 37.5.13. I2CxBTOC 37.5.14. [I2CxADB0] 37.5.15. I2CxADB1 37.5.16. I2CxADR0 37.5.17. I2CxADR1 37.5.18. I2CxADR2 37.5.19. I2CxADR3 37.5.20. I2CxTXB 37.5.21. I2CxRXB 37.6. Register Summary - I2C 38. CAN FD - Controller Area Network, Flexible Data-Rate 38.1. Module Overview 38.1.1. Module Functionality 38.2. Modes of Operation 38.2.1. Mode Change 38.2.1.1. Changing Between Normal Modes 38.2.1.2. Changing Between Debug Modes 38.2.1.3. Exiting Normal Mode 38.2.1.4. Entering and Exiting Disable Mode 38.2.1.5. Bus Integrating Mode 38.2.2. Configuration Mode 38.2.3. Normal Modes 38.2.3.1. Normal CAN FD Mode 38.2.3.2. Normal CAN 2.0 Mode 38.2.4. Disable Mode 38.2.5. Debug Modes 38.2.5.1. Listen Only Mode 38.2.5.2. Restricted Operation Mode 38.2.5.3. Loopback Mode 38.2.5.3.1. Internal Loopback Mode 38.2.5.3.2. External Loopback Mode 38.2.6. Low-Power Modes 38.2.6.1. Sleep Mode 38.2.6.2. Idle Mode 38.2.6.3. Wake-Up From Sleep 38.3. Configuration 38.3.1. Clock Configuration 38.3.2. CAN Configuration 38.3.2.1. ISO CRC Enable 38.3.2.2. Protocol Exception Disable 38.3.2.3. Wake-up Filter 38.3.2.4. Restriction of Transmission Attempts 38.3.2.5. Error State Indicator (ESI) in Gateway Mode 38.3.2.6. Mode Selection In Case of System Error 38.3.2.7. Reserving Message Memory for TXQ and TEF 38.3.3. CAN FD Bit Time Configuration 38.3.3.1. Sample Point 38.3.3.2. Propagation Delay 38.3.3.3. Transmitter Delay Compensation (TDC) 38.3.3.4. Synchronization 38.3.3.5. Synchronization Jump Width 38.3.3.6. Oscillator Tolerance 38.3.3.7. Recommendations for Bit Time Configuration 38.3.3.8. Bit Time Configuration Example 38.3.4. Message Memory Configuration 38.3.4.1. Transmit Event FIFO Configuration 38.3.4.2. Transmit Queue Configuration 38.3.4.3. Transmit FIFO Configuration 38.3.4.4. Receive FIFO Configuration 38.3.4.5. Calculation of Required Message Memory 38.4. CAN FD Message Frames 38.4.1. ISO vs. Non-ISO CRC 38.4.1.1. DLC Encoding 38.5. Message Transmission 38.5.1. Transmit Message Object 38.5.2. Loading Messages into Transmit FIFO 38.5.3. Loading Messages Into Transmit Queue 38.5.4. Requesting Transmission of Message in Transmit FIFO 38.5.5. Requesting Transmission of Message in Transmit Queue 38.5.6. C1TXREQ Register 38.5.7. Transmit Priority 38.5.7.1. Transmit Priority of Messages in FIFO 38.5.7.2. Transmit Priority of Messages in TXQ 38.5.7.3. Transmit Priority Based on ID 38.5.8. Transmit Bandwidth Sharing 38.5.9. Retransmission Attempts 38.5.9.1. Retransmission Attempts Disabled 38.5.9.2. Three Retransmission Attempts 38.5.9.3. Unlimited Retransmission 38.5.10. Aborting Transmission 38.5.11. Remote Transmit Request (RTR) 38.5.12. Mismatch of DLC and Payload Size During Transmission 38.5.13. Transmit State Diagram 38.5.14. Resetting Transmit FIFO 38.5.15. Resetting Transmit Queue 38.6. Transmit Event FIFO (TEF) 38.6.1. Reading a TEF Object 38.6.1.1. Resetting the TEF 38.7. Message Filtering 38.7.1. Filter Configuration 38.7.2. Filtering a Received Message 38.7.2.1. Filtering Standard or Extended Frames 38.7.2.2. Mask Bits 38.7.2.3. Filtering on Data Bytes 38.7.2.4. 12-Bit Standard ID 38.8. Message Reception 38.8.1. Receive Message Object 38.8.1.1. Reading a Receive Message Object 38.8.2. Receive State Diagram 38.8.3. Resetting RX FIFO 38.8.4. Mismatch of DLC and Payload Size During Reception 38.9. FIFO Behavior 38.9.1. FIFO Status Flags 38.9.1.1. TX FIFO Status Flags 38.9.1.2. RX FIFO Status Flags 38.9.1.3. TXQ Status Flags 38.9.1.4. TEF Status Flags 38.9.2. Transmit FIFO Behavior 38.9.3. Receive FIFO Behavior 38.9.4. Transmit Queue Behavior 38.9.5. Transmit Event FIFO Behavior 38.10. Timestamping 38.11. Interrupts 38.11.1. FIFO Individual Interrupts 38.11.1.1. Transmit Queue Interrupts 38.11.1.2. Receive FIFO Interrupts (RFIF) 38.11.1.3. Transmit FIFO Interrupts (TFIF) 38.11.1.4. Receive FIFO Overrun Interrupt (RXOVIF) 38.11.1.5. Transmit FIFO Attempt Interrupt (TXATIF) 38.11.1.6. Transmit Event FIFO Interrupts (TEFIF) 38.11.2. FIFO Combined Interrupts 38.11.3. Main Interrupts 38.11.3.1. Invalid Message Interrupt - IVMIF 38.11.3.2. Wake-Up Interrupt (WAKIF) 38.11.3.3. CAN Bus Error Interrupt (CERRIF) 38.11.3.4. CAN Mode Change Interrupt (MODIF) 38.11.3.5. CAN Timer Interrupt (TBCIF) 38.11.3.6. System Error Interrupt (SERRIF) 38.11.4. Interrupt Handling 38.11.4.1. Interrupt Look-up Table 38.11.4.2. Interrupt Status Register 38.11.5. Interrupt Flags 38.12. Error Handling 38.12.1. Bus Diagnostic Registers 38.12.2. Recovery from Bus Off State 38.13. Register Definitions: CAN FD Control 38.13.1. CxCON 38.13.2. CxNBTCFG 38.13.3. CxDBTCFG 38.13.4. CxTDC 38.13.5. CxTBC 38.13.6. CxTSCON 38.13.7. CxVEC 38.13.8. CxINT 38.13.9. CxRXIF 38.13.10. CxTXIF 38.13.11. CxRXOVIF 38.13.12. CxTXATIF 38.13.13. CxTXREQ 38.13.14. CxTREC 38.13.15. CxBDIAG0 38.13.16. CxBDIAG1 38.13.17. CxTEFCON 38.13.18. CxTEFSTA 38.13.19. CxTEFUA 38.13.20. CxFIFOBA 38.13.21. CxTXQCON 38.13.22. CxTXQSTA 38.13.23. CxTXQUA 38.13.24. CxFIFOCONy 38.13.25. CxFIFOSTAy 38.13.26. CxFIFOUAy 38.13.27. CxFLTCON0 38.13.28. CxFLTCON1 38.13.29. CxFLTCON2 38.13.30. CxFLTOBJy 38.13.31. CxMASKy 38.14. Register Summary - CAN FD 39. JTAG Boundary Scan 39.1. Test Access Port (TAP) and TAP Controller 39.1.1. TAP 39.1.2. TAP Controller 39.2. JTAG Registers 39.2.1. Instruction Shift Register and Instruction Register 39.2.2. Data Registers 39.3. Boundary Scan Register (BSR) 39.3.1. Boundary Scan Cell (BSC) 39.4. JTAG Instructions 39.5. Boundary Scan Testing 39.5.1. Related JTAG Files 39.6. Effects of Reset 40. HLVD - High/Low-Voltage Detect 40.1. Operation 40.2. Setup 40.3. Current Consumption 40.4. HLVD Start-up Time 40.5. Applications 40.6. Operation During Sleep 40.7. Operation During Idle and Doze Modes 40.8. Effects of a Reset 40.9. Register Definitions: HLVD Control 40.9.1. HLVDCON0 40.9.2. HLVDCON1 40.10. Register Summary - HLVD 41. FVR - Fixed Voltage Reference 41.1. Independent Gain Amplifiers 41.2. FVR Stabilization Period 41.3. Register Definitions: FVR 41.3.1. FVRCON 41.4. Register Summary - FVR 42. Temperature Indicator Module 42.1. Module Operation 42.1.1. Temperature Indicator Range 42.1.2. Minimum Operating VDD 42.2. Temperature Calculation 42.2.1. Higher-Order Calibration 42.3. ADC Acquisition Time 42.4. Register Definitions: Temperature Indicator 42.4.1. FVRCON 42.5. Register Summary - Temperature Indicator 43. ADC - Analog-to-Digital Converter with Computation and Context Module 43.1. ADC Configuration 43.1.1. Port Configuration 43.1.2. Channel Selection 43.1.3. ADC Voltage Reference 43.1.4. Conversion Clock 43.1.5. Interrupts 43.1.6. Result Formatting 43.2. ADC Operation 43.2.1. Starting a Conversion 43.2.2. Completion of a Conversion 43.2.3. ADC Operation During Sleep 43.2.4. External Trigger During Sleep 43.2.5. Auto-Conversion Trigger 43.2.6. ADC Conversion Procedure (Basic Mode) 43.3. ADC Acquisition Requirements 43.4. ADC Charge Pump 43.5. Computation Operation 43.5.1. Digital Filter/Average 43.5.2. Basic Mode 43.5.3. Accumulate Mode 43.5.4. Average Mode 43.5.5. Burst Average Mode 43.5.6. Low-Pass Filter Mode 43.5.7. Threshold Comparison 43.5.8. Repetition and Sampling Options 43.5.8.1. Continuous Sampling Mode 43.5.8.2. Double Sample Conversion 43.5.9. Capacitive Voltage Divider (CVD) Features 43.5.9.1. CVD Operation 43.5.9.2. Precharge Control 43.5.9.3. Acquisition Control for CVD (ADPRE > 0) 43.5.9.4. Guard Ring Outputs 43.5.9.5. Additional Sample-and-Hold Capacitance 43.6. Channel Sequencer and Context 43.6.1. Channel Context 43.6.1.1. Channel Context Configuration 43.6.1.2. Channel Context Configuration Example 43.6.2. Channel Sequencer 43.6.2.1. DMA Access 43.6.2.2. Channel Sequencer Configuration Examples 43.7. Register Definitions: ADC Control 43.7.1. ADCON0 43.7.2. ADCON1 43.7.3. ADCON2 43.7.4. ADCON3 43.7.5. ADSTAT 43.7.6. ADCLK 43.7.7. ADREF 43.7.8. ADPCH 43.7.9. ADPRE 43.7.10. ADACQ 43.7.11. ADCAP 43.7.12. ADRPT 43.7.13. ADCNT 43.7.14. ADFLTR 43.7.15. ADRES 43.7.16. ADPREV 43.7.17. ADACC 43.7.18. ADSTPT 43.7.19. ADERR 43.7.20. ADLTH 43.7.21. ADUTH 43.7.22. ADACT 43.7.23. ADCP 43.7.24. ADCTX 43.7.25. ADCSELx 43.8. Register Summary - ADC 44. DAC - Digital-to-Analog Converter Module 44.1. Output Voltage Selection 44.2. Ratiometric Output Level 44.3. Operation During Sleep 44.4. Effects of a Reset 44.5. Register Definitions: DAC Control 44.5.1. DACxCON 44.5.2. DACxDATL 44.6. Register Summary - DAC 45. CMP - Comparator Module 45.1. Comparator Overview 45.2. Comparator Control 45.2.1. Comparator Enable 45.2.2. Comparator Output 45.2.3. Comparator Output Polarity 45.3. Comparator Output Synchronization 45.4. Comparator Hysteresis 45.5. Comparator Interrupt 45.6. Comparator Positive Input Selection 45.7. Comparator Negative Input Selection 45.8. Comparator Response Time 45.9. Analog Input Connection Considerations 45.10. Operation in Sleep Mode 45.11. ADC Auto-Trigger Source 45.12. Register Definitions: Comparator Control 45.12.1. CMxCON0 45.12.2. CMxCON1 45.12.3. CMxNCH 45.12.4. CMxPCH 45.12.5. CMOUT 45.13. Register Summary - Comparator 46. ZCD - Zero-Cross Detection Module 46.1. External Resistor Selection 46.2. ZCD Logic Output 46.3. ZCD Logic Polarity 46.4. ZCD Interrupts 46.5. Correction for ZCPINV Offset 46.5.1. Correction by AC Coupling 46.5.2. Correction By Offset Current 46.6. Handling VPEAK Variations 46.7. Operation During Sleep 46.8. Effects of a Reset 46.9. Disabling the ZCD Module 46.10. Register Summary: ZCD 46.11. Register Definitions: ZCD Control 46.11.1. ZCDCON 47. Instruction Set Summary 47.1. Standard Instruction Set 47.1.1. Standard Instruction Set 47.2. Extended Instruction Set 47.2.1. Extended Instruction Syntax 47.2.2. Extended Instruction Set 47.2.3. Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode 47.2.3.1. Extended Instruction Syntax with Standard PIC18 Commands 47.2.4. Considerations when Enabling the Extended Instruction Set 47.2.5. Special Considerations with Microchip MPLAB® IDE Tools 48. ICSP™ - In-Circuit Serial Programming™ 48.1. High-Voltage Programming Entry Mode 48.2. Low-Voltage Programming Entry Mode 48.3. Common Programming Interfaces 49. Register Summary 50. Electrical Specifications 50.1. Absolute Maximum Ratings(†) 50.2. Standard Operating Conditions 50.3. DC Characteristics 50.3.1. Supply Voltage 50.3.2. Supply Current (IDD)(1,2,4) 50.3.3. Power-Down Current (IPD)(1,2) 50.3.4. I/O Ports 50.3.5. Memory Programming Specifications 50.3.6. Thermal Characteristics 50.4. AC Characteristics 50.4.1. External Clock/Oscillator Timing Requirements 50.4.2. Internal Oscillator Parameters(1) 50.4.3. PLL Specifications 50.4.4. I/O and CLKOUT Timing Specifications 50.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 50.4.6. High/Low-Voltage Detect Characteristics 50.4.7. Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) 50.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 50.4.9. Comparator Specifications 50.4.10. 8-Bit DAC Specifications 50.4.11. Fixed Voltage Reference (FVR) Specifications 50.4.12. Zero-Cross Detect (ZCD) Specifications 50.4.13. Timer0 and Timer1 External Clock Requirements 50.4.14. Capture/Compare/PWM Requirements (CCP) 50.4.15. SPI Mode Requirements 50.4.16. I2C Bus Start/Stop Bits Requirements 50.4.17. I2C Bus Data Requirements 50.4.18. Configurable Logic Cell (CLC) Characteristics 50.4.19. Temperature Indicator Requirements 51. DC and AC Characteristics Graphs and Tables 52. Packaging Information 52.1. Package Details 53. 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