Datasheet SAMA5D2 (Microchip) - 4

SAMA5D2 Series Description 1. Description
The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the Arm Cortex-A5 processor. It integrates the Arm NEON SIMD engine for accelerated multimedia and signal processing, a configurable 128-Kbyte L2 cache and a floating point unit (FPU) for high-precision computing. The device features an advanced user interface and connectivity peripherals. Advanced security is provided by powerful cryptographic accelerators, by the Arm TrustZone technology securing access to memories and sensitive peripherals, and by several hardware features that safeguard memory content, authenticate software, detect physical attacks and prevent information leakage during code execution. The SAMA5D2 features an internal multilayer bus architecture associated with 2 x 16 DMA channels and dedicated DMAs for the communication and interface peripherals required to ensure uninterrupted data transfers with minimal processor overhead. The device supports DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, QSPI and e.MMC Flash, and SLC/MLC parallel NAND Flash memory up to 32-bit ECC. The comprehensive peripheral set includes an LCD TFT controller with overlays for hardware-accelerated image composition, an image sensor controller, audio support through I2S, SSC, a stereo Class D amplifier and a digital microphone. Connectivity peripherals include a 10/100 EMAC, USBs, CANs, FLEXCOMs, UARTs, SPIs and two QSPIs, SDIO/SD/e.MMCs, and TWIs/I2C. Protection of code and data is provided by automatic scrambling of memories and an Integrity Check Monitor (ICM) to detect any modification of the memory contents. The SAMA5D2 also supports execution of encrypted code (QSPI or one portion of the DDR) with an “on-the-fly” encryption-decryption process. With its secure design architecture, cryptographic acceleration engines, and secure bootloader, the SAMA5D2 is the ideal solution for point-of-sale (POS), IoT and industrial applications requiring device authentication, anti-cloning, data protection and secure communication. SAMA5D2 devices feature three software-selectable low-power modes: Idle, Ultra-Low-Power and Backup. In Idle mode, the processor is stopped while all other functions can be kept running. In Ultra-Low-Power mode 0, the processor is stopped while all other functions are clocked at 512 Hz and interrupts or peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up (SleepWalking). In Ultra-Low-Power mode 1, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on events, including partial asynchronous wake-up (SleepWalking). In Backup mode, RTC and wake-up logic are active. The Backup mode can be extended to feature DDR in Self- refresh mode. SAMA5D2 devices also include an Event System that allows peripherals to receive, react to and send events in Active and Idle modes without processor intervention. © 2020 Microchip Technology Inc.
Complete Datasheet
DS60001476F-page 4 Document Outline Introduction Features 1. Description 2. Configuration Summary 3. Block Diagram 4. Signal Description 5. Microchip Recommended Power Management Solutions 5.1. MCP16502 PMIC 5.2. MCP16501 PMIC 6. Safety and Security Features 6.1. Design for Safety and IEC60730 Class B Certification 6.1.1. Background Information 6.2. Design for Security 6.3. Safety and IEC 60730 Features 6.4. Security Features 7. Package and Pinout 7.1. Packages 7.2. Pinouts 8. Power Considerations 8.1. Power Supplies 8.2. Power-up Considerations 8.3. Power-down Considerations 8.4. Power Supply Sequencing at Backup Mode Entry and Exit 8.4.1. VDDBU Power Architecture 8.4.2. Backup Mode Entry 8.4.3. Backup Mode Exit (Wake-up) 9. Memories 9.1. Embedded Memories 9.1.1. Internal SRAM 9.1.2. Internal ROM 9.1.3. Boot Strategies 9.2. External Memory 9.2.1. External Bus Interface 9.2.2. Supported Memories on DDR Interface 9.2.3. Supported Memories on Static Memories and NAND Flash Interfaces 9.2.4. DDR and SDMMC I/Os Calibration 9.2.4.1. DDR I/O Calibration 9.2.4.1.1. LPDDR2 Power Fail Management 9.2.4.2. SDMMC I/O Calibration 10. Event System 10.1. Real-time Event List 10.2. Real-time Event Mapping 11. System Controller 11.1. Power-On Reset 12. Peripherals 12.1. Peripheral Mapping 12.2. Peripheral Identifiers 12.3. Peripheral Signal Multiplexing on I/O Lines 12.4. Peripheral Clock Types 13. Chip Identifier (CHIPID) 13.1. Description 13.2. Embedded Characteristics 13.3. Register Summary 13.3.1. Chip ID Register 13.3.2. Chip ID Extension Register 14. Cortex-A5 Processor (ARM) 14.1. Reference Documents 14.2. Description 14.2.1. Power Management 14.2.1.1. Run Mode 14.2.1.2. Standby Mode 14.3. Embedded Characteristics 14.4. Block Diagram 14.5. Programmer Model 14.5.1. Processor Operating Modes 14.5.2. Processor Operating States 14.5.2.1. Switching State 14.5.3. Cortex-A5 Registers 14.5.3.1. CP15 Coprocessor 14.5.4. CP15 Register Access 14.5.5. Addresses in the Cortex-A5 Processor 14.5.6. Security Extensions Overview 14.5.6.1. System Boot Sequence 14.5.7. TrustZone 14.5.7.1. Hardware 14.5.7.2. Software 14.5.7.3. Debug 14.6. Memory Management Unit (MMU) 14.6.1. About the MMU 14.6.2. Memory Management System 14.6.2.1. Memory Types 14.6.3. Translation Lookaside Buffer (TLB) Organization 14.6.3.1. Micro TLB 14.6.3.2. Main TLB 14.6.4. Memory Access Sequence 14.6.5. Interaction with Memory System 14.6.6. External Aborts 14.6.6.1. External Aborts on Data Write 14.6.6.2. Synchronous and Asynchronous Aborts 14.6.7. MMU Software Accessible Registers 15. L2 Cache Controller (L2CC) 15.1. Description 15.2. Embedded Characteristics 15.3. Product Dependencies 15.3.1. Power Management 15.4. Functional Description 15.4.1. Double Linefill Issuing 15.5. Register Summary 15.5.1. L2CC Cache ID Register 15.5.2. L2CC Type Register 15.5.3. L2CC Control Register 15.5.4. L2CC Auxiliary Control Register 15.5.5. L2CC Tag RAM Latency Control Register 15.5.6. L2CC Data RAM Latency Control Register 15.5.7. L2CC Event Counter Control Register 15.5.8. L2CC Event Counter 1 Configuration Register 15.5.9. L2CC Event Counter 0 Configuration Register 15.5.10. L2CC Event Counter 1 Value Register 15.5.11. L2CC Event Counter 0 Value Register 15.5.12. L2CC Interrupt Mask Register 15.5.13. L2CC Masked Interrupt Status Register 15.5.14. L2CC Raw Interrupt Status Register 15.5.15. L2CC Interrupt Clear Register 15.5.16. L2CC Cache Synchronization Register 15.5.17. L2CC Invalidate Physical Address Line Register 15.5.18. L2CC Invalidate Way Register 15.5.19. L2CC Clean Physical Address Line Register 15.5.20. L2CC Clean Index Register 15.5.21. L2CC Clean Way Register 15.5.22. L2CC Clean Invalidate Physical Address Line Register 15.5.23. L2CC Clean Invalidate Index Register 15.5.24. L2CC Clean Invalidate Way Register 15.5.25. L2CC Data Lockdown Register 15.5.26. L2CC Instruction Lockdown Register 15.5.27. L2CC Debug Control Register 15.5.28. L2CC Prefetch Control Register 15.5.29. L2CC Power Control Register 16. Debug and Test Features 16.1. Description 16.2. Embedded Characteristics 16.3. Debug and Test Block Diagrams 16.4. Application Examples 16.4.1. Debug Environment 16.4.2. Test Environment 16.5. Debug and Test Pin Description 16.6. Functional Description 16.6.1. Test Pin 16.6.2. EmbeddedICE 16.6.3. JTAG Signal Description 16.6.4. IEEE 1149.1 JTAG Boundary Scan 16.7. Boundary JTAG ID Register 16.8. Cortex-A5 DP Identification Code Register IDCODE 16.8.1. JTAG Debug Port (JTAG-DP) 16.8.2. Serial Wire Debug Port (SW-DP) 17. Standard Boot Strategies 17.1. Description 17.2. Chip Access Using JTAG Connection 17.3. Flow Diagram 17.4. Chip Setup 17.5. Boot Configuration 17.5.1. Boot Configuration Word 17.5.2. Boot Sequence Controller Configuration Register 17.5.3. Backup Registers (BUREG) 17.5.4. Boot Configuration Word 17.5.5. NVM Boot Sequence 17.5.6. Valid Code Detection 17.5.6.1. Arm Exception Vectors Check 17.5.6.2. boot.bin File Check 17.5.7. Detailed Memory Boot Procedures 17.5.7.1. NAND Flash Boot: NAND Flash Detection 17.5.7.1.1. NAND Flash Specific Header Detection (Recommended Solution) 17.5.7.1.1.1. NAND Flash PMECC Register 17.5.7.1.1.2. ONFI 2.2 Parameters (Not Recommended) 17.5.7.2. NAND Flash Boot: PMECC Error Detection and Correction 17.5.7.3. SDCard/e.MMC Boot 17.5.7.4. SPI Flash Boot 17.5.7.4.1. Supported DataFlash Devices 17.5.7.4.2. Supported Serial Flash Devices 17.5.7.5. QSPI NOR Flash Boot for MRL A and MRL B 17.5.7.5.1. Definitions (MRL A, MRL B) 17.5.7.5.2. Supported QSPI Memory Manufacturers (MRL A, MRL B) 17.5.7.5.3. SPI Clock Frequency, Phase and Polarity (MRL A, MRL B) 17.5.7.5.4. QSPI Memory Detection (MRL A, MRL B) 17.5.7.5.5. Allowing Quad I/O Commands (MRL A, MRL B) 17.5.7.5.6. Configuration of Fast Read Quad I/O (EBh) Operations (MRL A, MRL B) 17.5.7.5.7. Miscellaneous Information (MRL A, MRL B) 17.5.7.6. QSPI NOR Flash Boot for MRL C 17.5.7.6.1. Supported QSPI Memories by Manufacturer (MRL C) 17.5.7.6.2. Hardware Considerations (MRL C) 17.5.7.6.3. Software Considerations (MRL C) 17.5.7.6.3.1. QSPI NOR memories with SFDP (JEDEC JESD216x compliant) 17.5.7.6.3.2. QSPI NOR memories without SFDP 17.5.8. Hardware and Software Constraints 17.6. SAM-BA Monitor 17.6.1. Command List 17.6.2. UART Port 17.6.3. Xmodem Protocol 17.6.4. USB Device Port 17.6.4.1. Supported External Crystal/External Clocks 17.6.4.2. USB Class 17.6.4.3. Enumeration Process 17.6.4.4. Communication Endpoints 17.7. Fuse Box Controller 17.7.1. Fuse Bit Mapping 18. AXI Matrix (AXIMX) 18.1. Description 18.2. Embedded Characteristics 18.3. Operation 18.3.1. Remap 18.4. Register Summary 18.4.1. AXI Matrix Remap Register 19. Matrix (H64MX/H32MX) 19.1. Description 19.2. Embedded Characteristics 19.3. 64-bit Matrix (H64MX) 19.3.1. Matrix Masters 19.3.2. Matrix Slaves 19.3.3. Master to Slave Access 19.4. 32-bit Matrix (H32MX) 19.4.1. Matrix Masters 19.4.2. Matrix Slaves 19.4.3. Master to Slave Access 19.5. Memory Mapping 19.6. Special Bus Granting Mechanism 19.7. No Default Master 19.8. Last Access Master 19.9. Fixed Default Master 19.10. Arbitration 19.10.1. Arbitration Scheduling 19.10.1.1. Undefined Length Burst Arbitration 19.10.1.2. Slot Cycle Limit Arbitration 19.10.2. Arbitration Priority Scheme 19.10.2.1. Fixed Priority Arbitration 19.10.2.2. Round-robin Arbitration 19.11. Register Write Protection 19.12. TrustZone Technology 19.12.1. Security Types of Slaves 19.12.1.1. Principles 19.12.1.2. Examples 19.12.2. Security Types of SDMMC System Bus Slaves 19.12.3. Security Types of System Bus Masters 19.12.4. Security of Peripheral Bus Slaves 19.13. Register Summary 19.13.1. Bus Matrix Master Configuration Registers 19.13.2. Bus Matrix Slave Configuration Registers 19.13.3. Bus Matrix Priority Registers A For Slaves 19.13.4. Bus Matrix Priority Registers B For Slaves 19.13.5. Master Error Interrupt Enable Register 19.13.6. Master Error Interrupt Disable Register 19.13.7. Master Error Interrupt Mask Register 19.13.8. Master Error Status Register 19.13.9. Master Error Address Registers 19.13.10. Write Protection Mode Register 19.13.11. Write Protection Status Register 19.13.12. Security Slave Registers 19.13.13. Security Areas Split Slave Registers 19.13.14. Security Region Top Slave Registers 19.13.15. Security Peripheral Select x Registers 20. Special Function Registers (SFR) 20.1. Description 20.2. Embedded Characteristics 20.3. Register Summary 20.3.1. DDR Configuration Register 20.3.2. OHCI Interrupt Configuration Register 20.3.3. OHCI Interrupt Status Register 20.3.4. Security Configuration Register 20.3.5. UTMI Clock Trimming Register 20.3.6. UTMI High-Speed Trimming Register 20.3.7. UTMI Full-Speed Trimming Register 20.3.8. UMTI DP/DM Pin Swapping Register 20.3.9. CAN Memories Address-based Register 20.3.10. Serial Number 0 Register 20.3.11. Serial Number 1 Register 20.3.12. AIC Interrupt Redirection Register 20.3.13. HRAMC L2CC Register 20.3.14. I2S Register 20.3.15. QSPI Clock Pad Supply Select Register 21. Special Function Registers Backup (SFRBU) 21.1. Description 21.2. Embedded Characteristics 21.3. Register Summary 21.3.1. SFRBU Power Switch BU Control Register 21.3.2. SFRBU Temperature Sensor Range Configuration Register 21.3.3. SFRBU DDR BU Mode Control Register 21.3.4. SFRBU RXLP Pull-Up Control Register 22. Advanced Interrupt Controller (AIC) 22.1. Description 22.2. Embedded Characteristics 22.3. Block Diagram 22.4. Application Block Diagram 22.5. AIC Detailed Block Diagram 22.6. I/O Line Description 22.7. Product Dependencies 22.7.1. I/O Lines 22.7.2. Power Management 22.7.3. Interrupt Sources 22.8. Functional Description 22.8.1. Interrupt Source Control 22.8.1.1. Interrupt Source Mode 22.8.1.2. Interrupt Source Enabling 22.8.1.3. Interrupt Clearing and Setting 22.8.1.4. Interrupt Status 22.8.1.5. Internal Interrupt Source Input Stage 22.8.1.6. External Interrupt Source Input Stage 22.8.2. Interrupt Latencies 22.8.2.1. External Interrupt Edge Triggered Source 22.8.2.2. External Interrupt Level Sensitive Source 22.8.2.3. Internal Interrupt Edge Triggered Source 22.8.2.4. Internal Interrupt Level Sensitive Source 22.8.3. Normal Interrupt 22.8.3.1. Priority Controller 22.8.3.2. Interrupt Nesting 22.8.3.3. Interrupt Handlers 22.8.4. Fast Interrupt 22.8.4.1. Fast Interrupt Source 22.8.4.2. Fast Interrupt Control 22.8.4.3. Fast Interrupt Handlers 22.8.5. Protect Mode 22.8.6. Spurious Interrupt 22.8.7. General Interrupt Mask 22.8.8. Register Write Protection 22.9. Register Summary 22.9.1. AIC Source Select Register 22.9.2. AIC Source Mode Register 22.9.3. AIC Source Vector Register 22.9.4. AIC Interrupt Vector Register 22.9.5. AIC FIQ Vector Register 22.9.6. AIC Interrupt Status Register 22.9.7. AIC Interrupt Pending Register 0 22.9.8. AIC Interrupt Pending Register 1 22.9.9. AIC Interrupt Pending Register 2 22.9.10. AIC Interrupt Pending Register 3 22.9.11. AIC Interrupt Mask Register 22.9.12. AIC Core Interrupt Status Register 22.9.13. AIC End of Interrupt Command Register 22.9.14. AIC Spurious Interrupt Vector Register 22.9.15. AIC Interrupt Enable Command Register 22.9.16. AIC Interrupt Disable Command Register 22.9.17. AIC Interrupt Clear Command Register 22.9.18. AIC Interrupt Set Command Register 22.9.19. AIC Debug Control Register 22.9.20. AIC Write Protection Mode Register 22.9.21. AIC Write Protection Status Register 23. Watchdog Timer (WDT) 23.1. Description 23.2. Embedded Characteristics 23.3. Block Diagram 23.4. Functional Description 23.5. Register Summary 23.5.1. Watchdog Timer Control Register 23.5.2. Watchdog Timer Mode Register 23.5.3. Watchdog Timer Status Register 24. Reset Controller (RSTC) 24.1. Description 24.2. Embedded Characteristics 24.3. Block Diagram 24.4. Functional Description 24.4.1. Reset Controller Overview 24.4.2. NRST Manager 24.4.2.1. NRST Signal or Interrupt 24.4.3. Reset States 24.4.3.1. General Reset 24.4.3.2. Wake-up Reset 24.4.3.3. User Reset 24.4.3.4. Software Reset 24.4.3.5. Watchdog Reset 24.4.4. Reset State Priorities 24.5. Register Summary 24.5.1. Reset Controller Control Register 24.5.2. Reset Controller Status Register 24.5.3. Reset Controller Mode Register 25. Shutdown Controller (SHDWC) 25.1. Description 25.2. Embedded Characteristics 25.3. Block Diagram 25.4. I/O Lines Description 25.5. Product Dependencies 25.5.1. Power Management 25.6. Functional Description 25.6.1. Wake-up Inputs 25.7. Register Summary 25.7.1. SHDWC Control Register 25.7.2. SHDWC Mode Register 25.7.3. SHDWC Status Register 25.7.4. SHDWC Wake-up Inputs Register 26. Periodic Interval Timer (PIT) 26.1. Description 26.2. Embedded Characteristics 26.3. Block Diagram 26.4. Functional Description 26.5. Register Summary 26.5.1. Periodic Interval Timer Mode Register 26.5.2. Periodic Interval Timer Status Register 26.5.3. Periodic Interval Timer Value Register 26.5.4. Periodic Interval Timer Image Register 27. Real-time Clock (RTC) 27.1. Description 27.2. Embedded Characteristics 27.3. Block Diagram 27.4. Product Dependencies 27.4.1. Power Management 27.4.2. Interrupt 27.5. Functional Description 27.5.1. Reference Clock 27.5.2. Timing 27.5.3. Alarm 27.5.4. Error Checking when Programming 27.5.5. RTC Internal Free-Running Counter Error Checking 27.5.6. Updating Time/Calendar 27.5.6.1. Gregorian and Persian Modes 27.5.6.2. UTC Mode 27.5.7. RTC Accurate Clock Calibration 27.5.8. Waveform Generation 27.5.9. Tamper Timestamping 27.6. Register Summary 27.6.1. RTC Control Register 27.6.2. RTC Mode Register 27.6.3. RTC Time Register 27.6.4. RTC Time Register (UTC_MODE) 27.6.5. RTC Calendar Register 27.6.6. RTC Time Alarm Register 27.6.7. RTC Time Alarm Register (UTC_MODE) 27.6.8. RTC Calendar Alarm Register 27.6.9. RTC Calendar Alarm Register (UTC_MODE) 27.6.10. RTC Status Register 27.6.11. RTC Status Clear Command Register 27.6.12. RTC Interrupt Enable Register 27.6.13. RTC Interrupt Disable Register 27.6.14. RTC Interrupt Mask Register 27.6.15. RTC Valid Entry Register 27.6.16. RTC TimeStamp Time Register 0 27.6.17. RTC TimeStamp Time Register 0 (UTC_MODE) 27.6.18. RTC TimeStamp Time Register 1 27.6.19. RTC TimeStamp Time Register 1 (UTC_MODE) 27.6.20. RTC TimeStamp Date Register 27.6.21. RTC TimeStamp Date Register (UTC_MODE) 27.6.22. RTC TimeStamp Source Register 28. System Controller Write Protection (SYSCWP) 28.1. Functional Description 28.1.1. System Controller Peripheral Mapping 28.1.2. Register Write Protection 28.2. Register Summary 28.2.1. SYSC Write Protection Mode Register 29. Slow Clock Controller (SCKC) 29.1. Description 29.2. Embedded Characteristics 29.3. Block Diagram 29.4. Functional Description 29.4.1. Switching from Embedded Always-on 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 29.4.2. Switching from 32.768 kHz Crystal Oscillator to Embedded Always-on 64 kHz RC Oscillator 29.5. Register Summary 29.5.1. Slow Clock Controller Configuration Register 30. Peripheral Touch Controller (PTC) 30.1. Description 30.2. Embedded Characteristics 30.3. Block Diagram 30.4. Signal Description 30.5. Product Dependencies 30.5.1. Power Management 30.5.2. I/O Lines 30.5.3. Interrupt Sources 30.6. Functional Description 30.6.1. picoPower Processor (pPP) 30.6.2. Shared Memories 30.6.2.1. Mailbox 30.6.2.2. SRAM Data Area 30.6.2.3. Firmware in SRAM Code Area 30.6.2.4. Host Interface 30.6.2.4.1. Processor Command Registers 30.6.3. PTC Digital Controller 30.6.3.1. PTC Digital Controller Operations 30.6.4. PTC Analog Front End (AFE) 30.6.5. Operations in Mutual Capacitance 30.6.6. Operations in Self-capacitance 30.7. Register Summary 30.7.1. PTC Command Register 30.7.2. PTC Interrupt Status Register 30.7.3. PTC Enable Register 31. Low Power Asynchronous Receiver (RXLP) 31.1. Description 31.2. Embedded Characteristics 31.3. Block Diagram 31.4. Product Dependencies 31.4.1. Power Management 31.5. Functional Description 31.5.1. Baud Rate Generator 31.5.2. Receiver 31.5.2.1. Receiver Reset, Enable and Disable 31.5.2.2. Start Detection and Data Sampling 31.5.2.3. Parity Error 31.5.2.4. Receiver Framing Error 31.5.2.5. Receiver Digital Filter 31.5.3. Comparison Function on Received Character 31.5.4. Register Write Protection 31.6. Register Summary 31.6.1. RXLP Control Register 31.6.2. RXLP Mode Register 31.6.3. RXLP Receiver Holding Register 31.6.4. RXLP Baud Rate Generator Register 31.6.5. RXLP Comparison Register 31.6.6. RXLP Write Protection Mode Register 32. Clock Generator 32.1. Description 32.2. Embedded Characteristics 32.3. Block Diagram 32.4. Slow Clock 32.4.1. Embedded 64 kHz (typical) RC Oscillator 32.4.2. 32.768 kHz Crystal Oscillator 32.5. Main Clock 32.5.1. 12 MHz RC Oscillator 32.5.2. 12 MHz RC Oscillator Clock Frequency Adjustment 32.5.3. 8 to 24 MHz Crystal Oscillator 32.5.4. Main Clock Source Selection 32.5.5. Bypassing the 8 to 24 MHz Crystal Oscillator 32.5.6. Main Frequency Counter 32.5.7. Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 32.6. Divider and PLLA Block 32.6.1. Divider and Phase Lock Loop Programming 32.7. UTMI PLL Clock 32.8. Audio PLL 33. Power Management Controller (PMC) 33.1. Description 33.2. Embedded Characteristics 33.3. Block Diagram 33.4. Master Clock Controller 33.5. Processor Clock Controller 33.6. Matrix Clock Controller 33.7. Programmable Clock Controller 33.8. Core and Bus Independent Clocks for Peripherals 33.9. Peripheral and Generic Clock Controller 33.10. LCDC Clock Controller 33.11. ISC Clock Controller 33.12. USB Device and Host Clocks 33.13. DDR2/LPDDR/LPDDR2 Clock Controller 33.14. Fast Start-up from Ultra-Low-Power (ULP) Mode 0 33.15. Fast Start-up from Ultra-Low-Power (ULP) Mode 1 33.16. Asynchronous Partial Wake-up (SleepWalking) 33.16.1. Description 33.16.2. Configuration Procedure 33.17. Main Crystal Oscillator Failure Detection 33.18. 32.768 kHz Crystal Oscillator Frequency Monitor 33.19. Programming Sequence 33.20. Clock Switching Details 33.20.1. Master Clock Switching Timings 33.20.2. Clock Switching Waveforms 33.21. Register Write Protection 33.22. Register Summary 33.22.1. PMC System Clock Enable Register 33.22.2. PMC System Clock Disable Register 33.22.3. PMC System Clock Status Register 33.22.4. PMC Peripheral Clock Enable Register 0 33.22.5. PMC Peripheral Clock Disable Register 0 33.22.6. PMC Peripheral Clock Status Register 0 33.22.7. PMC UTMI Clock Configuration Register 33.22.8. PMC Clock Generator Main Oscillator Register 33.22.9. PMC Clock Generator Main Clock Frequency Register 33.22.10. PMC Clock Generator PLLA Register 33.22.11. PMC Master Clock Register 33.22.12. PMC USB Clock Register 33.22.13. PMC Programmable Clock Register 33.22.14. PMC Interrupt Enable Register 33.22.15. PMC Interrupt Disable Register 33.22.16. PMC Status Register 33.22.17. PMC Interrupt Mask Register 33.22.18. PMC Fast Startup Polarity Register 33.22.19. PMC Fast Start-up Mode Register 33.22.20. PMC Fault Output Clear Register 33.22.21. PLL Charge Pump Current Register 33.22.22. PMC Write Protection Mode Register 33.22.23. PMC Write Protection Status Register 33.22.24. PMC Peripheral Clock Enable Register 1 33.22.25. PMC Peripheral Clock Disable Register 1 33.22.26. PMC Peripheral Clock Status Register 1 33.22.27. PMC Peripheral Control Register 33.22.28. PMC Oscillator Calibration Register 33.22.29. PMC SleepWalking Enable Register 0 33.22.30. PMC SleepWalking Disable Register 0 33.22.31. PMC SleepWalking Status Register 0 33.22.32. PMC SleepWalking Activity Status Register 0 33.22.33. PMC SleepWalking Enable Register 1 33.22.34. PMC SleepWalking Disable Register 1 33.22.35. PMC SleepWalking Status Register 1 33.22.36. PMC SleepWalking Activity Status Register 1 33.22.37. PMC SleepWalking Activity In Progress Register 33.22.38. PMC SleepWalking Control Register 33.22.39. PMC Audio PLL Control Register 0 33.22.40. PMC Audio PLL Control Register 1 34. Parallel Input/Output Controller (PIO) 34.1. Description 34.2. Embedded Characteristics 34.3. Block Diagram 34.4. Product Dependencies 34.4.1. Pin Multiplexing 34.4.2. External Interrupt Lines 34.4.3. Power Management 34.4.4. Interrupt Generation 34.5. Functional Description 34.5.1. I/O Line Configuration Method 34.5.1.1. Security Management 34.5.1.2. Programming I/O Line Configuration 34.5.1.3. Reading the I/O Line Configuration 34.5.2. Pull-Up and Pull-Down Resistor Control 34.5.3. General Purpose or Peripheral Function Selection 34.5.4. Output Control 34.5.5. Synchronous Data Output 34.5.6. Open-Drain Mode 34.5.7. Output Line Timings 34.5.8. Inputs 34.5.9. Input Glitch and Debouncing Filters 34.5.10. Input Edge/Level Interrupt 34.5.11. Interrupt Management 34.5.12. I/O Lines Lock 34.5.13. Programmable I/O Drive 34.5.14. Programmable Schmitt Trigger 34.5.15. I/O Line Configuration Freeze 34.5.15.1. Introduction 34.5.15.2. Software Freeze 34.5.15.2.1. Physical Freeze 34.5.15.2.2. Interrupt Freeze 34.5.16. Register Write Protection 34.6. I/O Lines Programming Example 34.7. Register Summary 34.7.1. PIO Mask Register 34.7.2. PIO Configuration Register 34.7.3. PIO Pin Data Status Register 34.7.4. PIO Lock Status Register 34.7.5. PIO Set Output Data Register 34.7.6. PIO Clear Output Data Register 34.7.7. PIO Output Data Status Register 34.7.8. PIO Interrupt Enable Register 34.7.9. PIO Interrupt Disable Register 34.7.10. PIO Interrupt Mask Register 34.7.11. PIO Interrupt Status Register 34.7.12. PIO I/O Freeze Configuration Register 34.7.13. PIO Write Protection Mode Register 34.7.14. PIO Write Protection Status Register 34.7.15. Secure PIO Mask Register 34.7.16. Secure PIO Configuration Register 34.7.17. Secure PIO Pin Data Status Register 34.7.18. Secure PIO Lock Status Register 34.7.19. Secure PIO Set Output Data Register 34.7.20. Secure PIO Clear Output Data Register 34.7.21. Secure PIO Output Data Status Register 34.7.22. Secure PIO Interrupt Enable Register 34.7.23. Secure PIO Interrupt Disable Register 34.7.24. Secure PIO Interrupt Mask Register 34.7.25. Secure PIO Interrupt Status Register 34.7.26. Secure PIO Set I/O Non-Secure Register 34.7.27. Secure PIO Set I/O Secure Register 34.7.28. Secure PIO I/O Security Status Register 34.7.29. Secure PIO I/O Freeze Configuration Register 34.7.30. Secure PIO Slow Clock Divider Debouncing Register 34.7.31. Secure PIO Write Protection Mode Register 34.7.32. Secure PIO Write Protection Status Register 35. External Memories 35.1. Multiport DDR-SDRAM Controller (MPDDRC) 35.1.1. Description 35.1.2. MPDDR Controller Block Diagram 35.1.3. IO Lines Description 35.1.4. Product Dependencies 35.1.5. Implementation Examples 35.1.5.1. 16-bit DDR2 35.1.5.2. 2x16-bit DDR2 35.1.5.3. 16-bit DDR3/DDR3L 35.1.5.4. 2x16-bit DDR3/DDR3L 35.1.5.5. 2x16-bit LPDDR2/LPDDR3 35.2. External Bus Interface (EBI) 35.2.1. Description 35.2.2. Implementation Examples 35.2.2.1. 8-bit NAND Flash 35.2.2.2. 16-bit NAND Flash 35.2.2.3. NOR Flash on NCS0 36. AHB Multiport DDR-SDRAM Controller (MPDDRC) 36.1. Description 36.2. Embedded Characteristics 36.3. Block Diagram 36.4. Product Dependencies, Initialization Sequence 36.4.1. Low-power DDR1-SDRAM Initialization 36.4.2. DDR2-SDRAM Initialization 36.4.3. Low-power DDR2-SDRAM Initialization 36.4.4. DDR3-SDRAM/DDR3L-SDRAM Initialization 36.4.5. Low-power DDR3-SDRAM Initialization 36.5. Functional Description 36.5.1. DDR-SDRAM Controller Write Cycle 36.5.2. DDR-SDRAM Controller Read Cycle 36.5.3. Refresh (Autorefresh Command) 36.5.3.1. All Banks Autorefresh 36.5.3.2. Per-bank Autorefresh 36.5.3.3. Adjust Autorefresh Rate 36.5.4. Power Management 36.5.4.1. Self-refresh Mode 36.5.4.2. Powerdown Mode 36.5.4.3. Deep Powerdown Mode 36.5.4.4. Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM Devices and DDR3-SDRAM 36.5.4.5. Reset Mode 36.5.5. Multiport Functionality 36.5.5.1. Round-robin Arbitration 36.5.5.2. Request-word Weighted Round-robin Arbitration 36.5.5.3. Bandwidth Weighted Round-robin Arbitration 36.5.6. Scrambling/Unscrambling Function 36.5.7. Register Write Protection 36.5.8. Monitor 36.6. Software Interface/SDRAM Organization, Address Mapping 36.6.1. DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width 36.6.2. DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 36.6.3. DDR-SDRAM Address Mapping for Low-cost Memories 36.7. Register Summary 36.7.1. MPDDRC Mode Register 36.7.2. MPDDRC Refresh Timer Register 36.7.3. MPDDRC Configuration Register 36.7.4. MPDDRC Timing Parameter 0 Register 36.7.5. MPDDRC Timing Parameter 1 Register 36.7.6. MPDDRC Timing Parameter 2 Register 36.7.7. MPDDRC Low-Power Register 36.7.8. MPDDRC Memory Device Register 36.7.9. MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register 36.7.10. MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register 36.7.11. MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register 36.7.12. MPDDRC I/O Calibration Register 36.7.13. MPDDRC OCMS Register 36.7.14. MPDDRC OCMS KEY1 Register 36.7.15. MPDDRC OCMS KEY2 Register 36.7.16. MPDDRC Configuration Arbiter Register 36.7.17. MPDDRC Timeout Register 36.7.18. MPDDRC Request Port 0-1-2-3 Register 36.7.19. MPDDRC Request Port 4-5-6-7 Register 36.7.20. MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 36.7.21. MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register 36.7.22. MPDDRC Read Data Path Register 36.7.23. MPDDRC Monitor Configuration Register 36.7.24. MPDDRC Monitor Address High/Low Port x Register 36.7.25. MPDDRC Monitor Information Port x Register (MAX_WAIT) 36.7.26. MPDDRC Monitor Information Port x Register (NB_TRANSFERS) 36.7.27. MPDDRC Monitor Information Port x Register (TOTAL_LATENCY) 36.7.28. MPDDRC Write Protection Mode Register 36.7.29. MPDDRC Write Protection Status Register 37. Static Memory Controller (SMC) 37.1. Description 37.2. Embedded Characteristics 37.3. Block Diagram 37.4. I/O Lines Description 37.5. Multiplexed Signals 37.6. Application Example 37.6.1. Hardware Interface 37.7. Product Dependencies 37.7.1. I/O Lines 37.7.2. Power Management 37.7.3. Interrupt Sources 37.8. External Memory Mapping 37.9. Connection to External Devices 37.9.1. Data Bus Width 37.9.2. Byte Write or Byte Select Access 37.9.2.1. Byte Write Access 37.9.2.2. Byte Select Access 37.9.2.3. Signal Multiplexing 37.10. Standard Read and Write Protocols 37.10.1. Read Waveforms 37.10.1.1. NRD Waveform 37.10.1.2. NCS Waveform 37.10.1.3. Read Cycle 37.10.2. Read Mode 37.10.2.1. Read is Controlled by NRD (READ_MODE = 1) 37.10.2.2. Read is Controlled by NCS (READ_MODE = 0) 37.10.3. Write Waveforms 37.10.3.1. NWE Waveforms 37.10.3.2. NCS Waveforms 37.10.3.3. Write Cycle 37.10.4. Write Mode 37.10.4.1. Write is Controlled by NWE (WRITE_MODE = 1) 37.10.4.2. Write is Controlled by NCS (WRITE_MODE = 0) 37.10.5. Coding Timing Parameters 37.10.6. Reset Values of Timing Parameters 37.10.7. Usage Restriction 37.10.7.1. For Read Operations 37.10.7.2. For Write Operations 37.10.7.3. For Read and Write Operations 37.11. Scrambling/Unscrambling Function 37.12. Automatic Wait States 37.12.1. Chip Select Wait States 37.12.2. Early Read Wait State 37.12.3. Reload User Configuration Wait State 37.12.3.1. User Procedure 37.12.3.2. Slow Clock Mode Transition 37.12.4. Read to Write Wait State 37.13. Data Float Wait States 37.13.1. READ_MODE 37.13.2. TDF Optimization Enabled (TDF_MODE = 1) 37.13.3. TDF Optimization Disabled (TDF_MODE = 0) 37.14. External Wait 37.14.1. Restriction 37.14.2. Frozen Mode 37.14.3. Ready Mode 37.14.4. NWAIT Latency and Read/Write Timings 37.15. Slow Clock Mode 37.15.1. Slow Clock Mode Waveforms 37.15.2. Switching from (to) Slow Clock Mode to (from) Normal Mode 37.16. Register Write Protection 37.17. NFC Operations 37.17.1. NFC Overview 37.17.2. NFC Control Registers 37.17.2.1. Building NFC Address Command Example 37.17.2.2. NFC Address Command 37.17.2.3. NFC Data Address 37.17.2.4. NFC Data Status 37.17.3. NFC Initialization 37.17.3.1. NFC Timing Engine 37.17.4. NFC SRAM 37.17.4.1. NFC SRAM Mapping 37.17.4.2. NFC SRAM Access Prioritization Algorithm 37.17.5. NAND Flash Operations 37.17.5.1. Page Read 37.17.5.2. Program Page 37.18. PMECC Controller Functional Description 37.18.1. MLC/SLC Write Page Operation Using PMECC 37.18.1.1. SLC/MLC Write Operation with Spare Enable Bit Set 37.18.1.2. SLC/MLC Write Operation with Spare Disable 37.18.2. MLC/SLC Read Page Operation Using PMECC 37.18.2.1. MLC/SLC Read Operation with Spare Decoding 37.18.2.2. MLC/SLC Read Operation 37.18.2.3. MLC/SLC User Read ECC Area 37.18.2.4. MLC Controller Working with NFC 37.19. Software Implementation 37.19.1. Remainder Substitution Procedure 37.19.2. Finding the Error Location Polynomial Sigma(x) 37.19.3. Finding the Error Position 37.19.3.1. Error Location 37.20. Register Summary 37.20.1. NFC Configuration Register 37.20.2. NFC Control Register 37.20.3. NFC Status Register 37.20.4. NFC Interrupt Enable Register 37.20.5. NFC Interrupt Disable Register 37.20.6. NFC Interrupt Mask Register 37.20.7. NFC Address Cycle Zero Register 37.20.8. NFC Bank Register 37.20.9. PMECC Configuration Register 37.20.10. PMECC Spare Area Size Register 37.20.11. PMECC Start Address Register 37.20.12. PMECC End Address Register 37.20.13. PMECC Control Register 37.20.14. PMECC Status Register 37.20.15. PMECC Interrupt Enable Register 37.20.16. PMECC Interrupt Disable Register 37.20.17. PMECC Interrupt Mask Register 37.20.18. PMECC Interrupt Status Register 37.20.19. PMECC Redundancy x Register 37.20.20. PMECC Remainder x Register 37.20.21. PMECC Error Location Configuration Register 37.20.22. PMECC Error Location Primitive Register 37.20.23. PMECC Error Location Enable Register 37.20.24. PMECC Error Location Disable Register 37.20.25. PMECC Error Location Status Register 37.20.26. PMECC Error Location Interrupt Enable Register 37.20.27. PMECC Error Location Interrupt Disable Register 37.20.28. PMECC Error Location Interrupt Mask Register 37.20.29. PMECC Error Location Interrupt Status Register 37.20.30. PMECC Error Location SIGMA0 Register 37.20.31. PMECC Error Location SIGMAx Register 37.20.32. PMECC Error Location x Register 37.20.33. Setup Register 37.20.34. Pulse Register 37.20.35. Cycle Register 37.20.36. Timings Register 37.20.37. Mode Register 37.20.38. Off Chip Memory Scrambling Register 37.20.39. Off Chip Memory Scrambling Key1 Register 37.20.40. Off Chip Memory Scrambling Key2 Register 37.20.41. Write Protection Mode Register 37.20.42. Write Protection Status Register 38. DMA Controller (XDMAC) 38.1. Description 38.2. Embedded Characteristics 38.3. Block Diagram 38.4. DMA Controller Peripheral Connections 38.5. Functional Description 38.5.1. Basic Definitions 38.5.2. Data Striding Diagram 38.5.3. Transfer Hierarchy Diagrams 38.5.4. Peripheral Synchronized Transfer 38.5.4.1. Peripheral to Memory Transfer 38.5.4.2. Memory to Peripheral Transfer 38.5.4.3. Software Triggered Synchronized Transfer 38.5.5. XDMAC Transfer Software Operation 38.5.5.1. Single Block Transfer With Single Microblock 38.5.5.2. Single Block Transfer With Multiple Microblock 38.5.5.3. Master Transfer 38.5.5.4. Disabling A Channel Before Transfer Completion 38.6. Linked List Descriptor Operation 38.6.1. Linked List Descriptor View 38.6.1.1. Channel Next Descriptor View 0–3 Structures 38.6.2. Descriptor Structure Members Description 38.6.2.1. Descriptor Structure Microblock Control Member 38.7. XDMAC Maintenance Software Operations 38.7.1. Disabling a Channel 38.7.2. Suspending a Channel 38.7.3. Flushing a Channel 38.7.4. Maintenance Operation Priority 38.7.4.1. Disable Operation Priority 38.7.4.2. Flush Operation Priority 38.7.4.3. Suspend Operation Priority 38.8. XDMAC Software Requirements 38.9. Register Summary 38.9.1. XDMAC Global Type Register 38.9.2. XDMAC Global Configuration Register 38.9.3. XDMAC Global Weighted Arbiter Configuration Register 38.9.4. XDMAC Global Interrupt Enable Register 38.9.5. XDMAC Global Interrupt Disable Register 38.9.6. XDMAC Global Interrupt Mask Register 38.9.7. XDMAC Global Interrupt Status Register 38.9.8. XDMAC Global Channel Enable Register 38.9.9. XDMAC Global Channel Disable Register 38.9.10. XDMAC Global Channel Status Register 38.9.11. XDMAC Global Channel Read Suspend Register 38.9.12. XDMAC Global Channel Write Suspend Register 38.9.13. XDMAC Global Channel Read Write Suspend Register 38.9.14. XDMAC Global Channel Read Write Resume Register 38.9.15. XDMAC Global Channel Software Request Register 38.9.16. XDMAC Global Channel Software Request Status Register 38.9.17. XDMAC Global Channel Software Flush Request Register 38.9.18. XDMAC Channel x Interrupt Enable Register [x=0..15] 38.9.19. XDMAC Channel x Interrupt Disable Register [x = 0..15] 38.9.20. XDMAC Channel x Interrupt Mask Register [x = 0..15] 38.9.21. XDMAC Channel x Interrupt Status Register [x = 0..15] 38.9.22. XDMAC Channel x Source Address Register [x = 0..15] 38.9.23. XDMAC Channel x Destination Address Register [x = 0..15] 38.9.24. XDMAC Channel x Next Descriptor Address Register [x = 0..15] 38.9.25. XDMAC Channel x Next Descriptor Control Register [x = 0..15] 38.9.26. XDMAC Channel x Microblock Control Register [x = 0..15] 38.9.27. XDMAC Channel x Block Control Register [x = 0..15] 38.9.28. XDMAC Channel x Configuration Register [x = 0..15] 38.9.29. XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..15] 38.9.30. XDMAC Channel x Source Microblock Stride Register [x = 0..15] 38.9.31. XDMAC Channel x Destination Microblock Stride Register [x = 0..15] 39. LCD Controller (LCDC) 39.1. Description 39.2. Embedded Characteristics 39.3. Block Diagram 39.4. I/O Lines Description 39.5. Product Dependencies 39.5.1. I/O Lines 39.5.2. Power Management 39.5.3. Interrupt Sources 39.6. Functional Description 39.6.1. Timing Engine Configuration 39.6.1.1. Pixel Clock Period Configuration 39.6.1.2. Horizontal and Vertical Synchronization Configuration 39.6.1.3. Timing Engine Powerup Software Operation 39.6.1.4. Timing Engine Powerdown Software Operation 39.6.2. DMA Software Operations 39.6.2.1. DMA Channel Descriptor (DSCR) Alignment and Structure 39.6.2.2. Enabling a DMA Channel 39.6.2.3. Disabling a DMA Channel 39.6.2.4. DMA Dynamic Linking of a New Transfer Descriptor 39.6.2.5. DMA Interrupt Generation 39.6.2.6. DMA Address Alignment Requirements 39.6.3. Overlay Software Configuration 39.6.3.1. System Bus Access Attributes 39.6.3.2. Color Attributes 39.6.3.3. Window Position, Size, Scaling and Striding Attributes 39.6.3.4. Overlay Blender Attributes 39.6.3.5. Overlay Attributes Software Operation 39.6.4. RGB Frame Buffer Memory Bitmap 39.6.4.1. 1 bpp Through Color Lookup Table 39.6.4.2. 2 bpp Through Color Lookup Table 39.6.4.3. 4 bpp Through Color Lookup Table 39.6.4.4. 8 bpp Through Color Lookup Table 39.6.4.5. 12 bpp Memory Mapping, RGB 4:4:4 39.6.4.6. 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 39.6.4.7. 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 39.6.4.8. 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 39.6.4.9. 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 39.6.4.10. 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 39.6.4.11. 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 39.6.4.12. 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 39.6.4.13. 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 39.6.4.14. 24 bpp Unpacked Memory Mapping, RGB 8:8:8 39.6.4.15. 24 bpp Packed Memory Mapping, RGB 8:8:8 39.6.4.16. 25 bpp Memory Mapping, ARGB 1:8:8:8 39.6.4.17. 32 bpp Memory Mapping, ARGB 8:8:8:8 39.6.4.18. 32 bpp Memory Mapping, RGBA 8:8:8:8 39.6.5. YUV Frame Buffer Memory Mapping 39.6.5.1. AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping 39.6.5.2. 4:2:2 Interleaved Mode Frame Buffer Memory Mapping 39.6.5.3. 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 39.6.5.4. 4:2:2 Planar Mode Frame Buffer Memory Mapping 39.6.5.5. 4:2:0 Planar Mode Frame Buffer Memory Mapping 39.6.5.6. 4:2:0 Semiplanar Frame Buffer Memory Mapping 39.6.6. Chrominance Upsampling Unit 39.6.6.1. Chrominance Upsampling Algorithm 39.6.7. Line and Pixel Striding 39.6.7.1. Line Striding 39.6.7.2. Pixel Striding 39.6.8. Color Space Conversion Unit 39.6.9. Two-Dimension Scaler 39.6.9.1. Video Scaler Description 39.6.9.2. Horizontal Scaler 39.6.9.3. Vertical Scaler 39.6.10. Color Combine Unit 39.6.10.1. Window Overlay 39.6.10.2. Base Layer with Window Overlay Optimization 39.6.10.3. Overlay Blending 39.6.10.4. Window Blending 39.6.10.5. Color Keying 39.6.10.5.1. Source Color Keying 39.6.10.5.2. Destination Color Keying 39.6.11. LCDC PWM Controller 39.6.12. Post Processing Controller 39.6.13. LCD Overall Performance 39.6.13.1. Color Lookup Table (CLUT) 39.6.13.2. RGB Mode Fetch Performance 39.6.13.3. YUV Mode Fetch Performance 39.6.14. Input FIFO 39.6.15. Output FIFO 39.6.16. Output Timing Generation 39.6.16.1. Active Display Timing Mode 39.6.17. Output Format 39.6.17.1. Active Mode Output Pin Assignment 39.7. Register Summary 39.7.1. LCD Controller Configuration Register 0 39.7.2. LCD Controller Configuration Register 1 39.7.3. LCD Controller Configuration Register 2 39.7.4. LCD Controller Configuration Register 3 39.7.5. LCD Controller Configuration Register 4 39.7.6. LCD Controller Configuration Register 5 39.7.7. LCD Controller Configuration Register 6 39.7.8. LCD Controller Enable Register 39.7.9. LCD Controller Disable Register 39.7.10. LCD Controller Status Register 39.7.11. LCD Controller Interrupt Enable Register 39.7.12. LCD Controller Interrupt Disable Register 39.7.13. LCD Controller Interrupt Mask Register 39.7.14. LCD Controller Interrupt Status Register 39.7.15. LCD Controller Attribute Register 39.7.16. Base Layer Channel Enable Register 39.7.17. Base Layer Channel Disable Register 39.7.18. Base Layer Channel Status Register 39.7.19. Base Layer Interrupt Enable Register 39.7.20. Base Layer Interrupt Disable Register 39.7.21. Base Layer Interrupt Mask Register 39.7.22. Base Layer Interrupt Status Register 39.7.23. Base DMA Head Register 39.7.24. Base DMA Address Register 39.7.25. Base DMA Control Register 39.7.26. Base DMA Next Register 39.7.27. Base Layer Configuration Register 0 39.7.28. Base Layer Configuration Register 1 39.7.29. Base Layer Configuration Register 2 39.7.30. Base Layer Configuration Register 3 39.7.31. Base Layer Configuration Register 4 39.7.32. Base Layer Configuration Register 5 39.7.33. Base Layer Configuration Register 6 39.7.34. Overlay 1 Channel Enable Register 39.7.35. Overlay 1 Channel Disable Register 39.7.36. Overlay 1 Channel Status Register 39.7.37. Overlay 1 Interrupt Enable Register 39.7.38. Overlay 1 Interrupt Disable Register 39.7.39. Overlay 1 Interrupt Mask Register 39.7.40. Overlay 1 Interrupt Status Register 39.7.41. Overlay 1 Head Register 39.7.42. Overlay 1 Address Register 39.7.43. Overlay 1 Control Register 39.7.44. Overlay 1 Next Register 39.7.45. Overlay 1 Configuration Register 0 39.7.46. Overlay 1 Configuration Register 1 39.7.47. Overlay 1 Configuration Register 2 39.7.48. Overlay 1 Configuration Register 3 39.7.49. Overlay 1 Configuration Register 4 39.7.50. Overlay 1 Configuration Register 5 39.7.51. Overlay 1 Configuration Register 6 39.7.52. Overlay 1 Configuration Register 7 39.7.53. Overlay 1 Configuration Register 8 39.7.54. Overlay 1 Configuration Register 9 39.7.55. Overlay 2 Channel Enable Register 39.7.56. Overlay 2 Channel Disable Register 39.7.57. Overlay 2 Channel Status Register 39.7.58. Overlay 2 Interrupt Enable Register 39.7.59. Overlay 2 Interrupt Disable Register 39.7.60. Overlay 2 Interrupt Mask Register 39.7.61. Overlay 2 Interrupt Status Register 39.7.62. Overlay 2 Head Register 39.7.63. Overlay 2 Address Register 39.7.64. Overlay 2 Control Register 39.7.65. Overlay 2 Next Register 39.7.66. Overlay 2 Configuration Register 0 39.7.67. Overlay 2 Configuration Register 1 39.7.68. Overlay 2 Configuration Register 2 39.7.69. Overlay 2 Configuration Register 3 39.7.70. Overlay 2 Configuration Register 4 39.7.71. Overlay 2 Configuration Register 5 39.7.72. Overlay 2 Configuration Register 6 39.7.73. Overlay 2 Configuration Register 7 39.7.74. Overlay 2 Configuration Register 8 39.7.75. Overlay 2 Configuration Register 9 39.7.76. High-End Overlay Channel Enable Register 39.7.77. High-End Overlay Channel Disable Register 39.7.78. High-End Overlay Channel Status Register 39.7.79. High-End Overlay Interrupt Enable Register 39.7.80. High-End Overlay Interrupt Disable Register 39.7.81. High-End Overlay Interrupt Mask Register 39.7.82. High-End Overlay Interrupt Status Register 39.7.83. High-End Overlay DMA Head Register 39.7.84. High-End Overlay DMA Address Register 39.7.85. High-End Overlay DMA Control Register 39.7.86. High-End Overlay DMA Next Register 39.7.87. High-End Overlay U-UV DMA Head Register 39.7.88. High-End Overlay U-UV DMA Address Register 39.7.89. High-End Overlay U-UV DMA Control Register 39.7.90. High-End Overlay U-UV DMA Next Register 39.7.91. High-End Overlay V DMA Head Register 39.7.92. High-End Overlay V DMA Address Register 39.7.93. High-End Overlay V DMA Control Register 39.7.94. High-End Overlay V DMA Next Register 39.7.95. High-End Overlay Configuration Register 0 39.7.96. High-End Overlay Configuration Register 1 39.7.97. High-End Overlay Configuration Register 2 39.7.98. High-End Overlay Configuration Register 3 39.7.99. High-End Overlay Configuration Register 4 39.7.100. High-End Overlay Configuration Register 5 39.7.101. High-End Overlay Configuration Register 6 39.7.102. High-End Overlay Configuration Register 7 39.7.103. High-End Overlay Configuration Register 8 39.7.104. High-End Overlay Configuration Register 9 39.7.105. High-End Overlay Configuration Register 10 39.7.106. High-End Overlay Configuration Register 11 39.7.107. High-End Overlay Configuration Register 12 39.7.108. High-End Overlay Configuration Register 13 39.7.109. High-End Overlay Configuration Register 14 39.7.110. High-End Overlay Configuration Register 15 39.7.111. High-End Overlay Configuration Register 16 39.7.112. High-End Overlay Configuration Register 17 39.7.113. High-End Overlay Configuration Register 18 39.7.114. High-End Overlay Configuration Register 19 39.7.115. High-End Overlay Configuration Register 20 39.7.116. High-End Overlay Configuration Register 21 39.7.117. High-End Overlay Configuration Register 22 39.7.118. High-End Overlay Configuration Register 23 39.7.119. High-End Overlay Configuration Register 24 39.7.120. High-End Overlay Configuration Register 25 39.7.121. High-End Overlay Configuration Register 26 39.7.122. High-End Overlay Configuration Register 27 39.7.123. High-End Overlay Configuration Register 28 39.7.124. High-End Overlay Configuration Register 29 39.7.125. High-End Overlay Configuration Register 30 39.7.126. High-End Overlay Configuration Register 31 39.7.127. High-End Overlay Configuration Register 32 39.7.128. High-End Overlay Configuration Register 33 39.7.129. High-End Overlay Configuration Register 34 39.7.130. High-End Overlay Configuration Register 35 39.7.131. High-End Overlay Configuration Register 36 39.7.132. High-End Overlay Configuration Register 37 39.7.133. High-End Overlay Configuration Register 38 39.7.134. High-End Overlay Configuration Register 39 39.7.135. High-End Overlay Configuration Register 40 39.7.136. High-End Overlay Configuration Register 41 39.7.137. Post Processing Channel Enable Register 39.7.138. Post Processing Channel Disable Register 39.7.139. Post Processing Channel Status Register 39.7.140. Post Processing Interrupt Enable Register 39.7.141. Post Processing Interrupt Disable Register 39.7.142. Post Processing Interrupt Mask Register 39.7.143. Post Processing Interrupt Status Register 39.7.144. Post Processing Head Register 39.7.145. Post Processing Address Register 39.7.146. Post Processing Control Register 39.7.147. Post Processing Next Register 39.7.148. Post Processing Configuration Register 0 39.7.149. Post Processing Configuration Register 1 39.7.150. Post Processing Configuration Register 2 39.7.151. Post Processing Configuration Register 3 39.7.152. Post Processing Configuration Register 4 39.7.153. Post Processing Configuration Register 5 39.7.154. Base CLUT Register x 39.7.155. Overlay 1 CLUT Register x 39.7.156. Overlay 2 CLUT Register x 39.7.157. High-End Overlay CLUT Register x 40. Ethernet MAC (GMAC) 40.1. Description 40.2. Embedded Characteristics 40.3. Block Diagram 40.4. Signal Interfaces 40.5. Product Dependencies 40.5.1. I/O Lines 40.5.2. Power Management 40.5.3. Interrupt Sources 40.6. Functional Description 40.6.1. Media Access Controller 40.6.2. 1588 Timestamp Unit 40.6.3. Direct Memory Access Interface 40.6.3.1. Packet Buffer DMA 40.6.3.2. Receive Buffers 40.6.3.3. Transmit Buffers 40.6.3.4. DMA Bursting on the System Bus 40.6.3.5. DMA Packet Buffer 40.6.3.6. Transmit Packet Buffer 40.6.3.7. Receive Packet Buffer 40.6.3.8. Priority Queueing in the DMA 40.6.4. MAC Transmit Block 40.6.5. MAC Receive Block 40.6.6. Checksum Offload for IP, TCP and UDP 40.6.6.1. Receiver Checksum Offload 40.6.6.2. Transmitter Checksum Offload 40.6.7. MAC Filtering Block 40.6.8. Broadcast Address 40.6.9. Hash Addressing 40.6.10. Copy all Frames (Promiscuous Mode) 40.6.11. Disable Copy of Pause Frames 40.6.12. VLAN Support 40.6.13. Wake on LAN Support 40.6.14. IEEE 1588 Support 40.6.15. Timestamp Unit 40.6.16. MAC 802.3 Pause Frame Support 40.6.16.1. 802.3 Pause Frame Reception 40.6.16.2. 802.3 Pause Frame Transmission 40.6.17. MAC PFC Priority-based Pause Frame Support 40.6.17.1. PFC Pause Frame Reception 40.6.17.2. PFC Pause Frame Transmission 40.6.18. Energy-efficient Ethernet Support 40.6.19. 802.1Qav Support - Credit-based Shaping 40.6.20. LPI Operation in the GMAC 40.6.21. PHY Interface 40.6.22. 10/100 Operation 40.6.23. Jumbo Frames 40.7. Programming Interface 40.7.1. Initialization 40.7.1.1. Configuration 40.7.1.2. Receive Buffer List 40.7.1.3. Transmit Buffer List 40.7.1.4. Address Matching 40.7.1.5. PHY Maintenance 40.7.1.6. Interrupts 40.7.1.7. Transmitting Frames 40.7.1.8. Receiving Frames 40.7.2. Statistics Registers 40.8. Register Summary 40.8.1. GMAC Network Control Register 40.8.2. GMAC Network Configuration Register 40.8.3. GMAC Network Status Register 40.8.4. GMAC User Register 40.8.5. GMAC DMA Configuration Register 40.8.6. GMAC Transmit Status Register 40.8.7. GMAC Receive Buffer Queue Base Address Register 40.8.8. GMAC Transmit Buffer Queue Base Address Register 40.8.9. GMAC Receive Status Register 40.8.10. GMAC Interrupt Status Register 40.8.11. GMAC Interrupt Enable Register 40.8.12. GMAC Interrupt Disable Register 40.8.13. GMAC Interrupt Mask Register 40.8.14. GMAC PHY Maintenance Register 40.8.15. GMAC Receive Pause Quantum Register 40.8.16. GMAC Transmit Pause Quantum Register 40.8.17. GMAC RX Jumbo Frame Max Length Register 40.8.18. GMAC Hash Register Bottom 40.8.19. GMAC Hash Register Top 40.8.20. GMAC Specific Address 1 Bottom Register 40.8.21. GMAC Specific Address 1 Top Register 40.8.22. GMAC Specific Address 2 Bottom Register 40.8.23. GMAC Specific Address 2 Top Register 40.8.24. GMAC Specific Address 3 Bottom Register 40.8.25. GMAC Specific Address 3 Top Register 40.8.26. GMAC Specific Address 4 Bottom Register 40.8.27. GMAC Specific Address 4 Top Register 40.8.28. GMAC Type ID Match 1 Register 40.8.29. GMAC Type ID Match 2 Register 40.8.30. GMAC Type ID Match 3 Register 40.8.31. GMAC Type ID Match 4 Register 40.8.32. GMAC Wake on LAN Register 40.8.33. GMAC IPG Stretch Register 40.8.34. GMAC Stacked VLAN Register 40.8.35. GMAC Transmit PFC Pause Register 40.8.36. GMAC Specific Address 1 Mask Bottom Register 40.8.37. GMAC Specific Address Mask 1 Top Register 40.8.38. GMAC 1588 Timer Nanosecond Comparison Register 40.8.39. GMAC 1588 Timer Second Comparison Low Register 40.8.40. GMAC 1588 Timer Second Comparison High Register 40.8.41. GMAC PTP Event Frame Transmitted Seconds High Register 40.8.42. GMAC PTP Event Frame Received Seconds High Register 40.8.43. GMAC PTP Peer Event Frame Transmitted Seconds High Register 40.8.44. GMAC PTP Peer Event Frame Received Seconds High Register 40.8.45. GMAC Octets Transmitted Low Register 40.8.46. GMAC Octets Transmitted High Register 40.8.47. GMAC Frames Transmitted Register 40.8.48. GMAC Broadcast Frames Transmitted Register 40.8.49. GMAC Multicast Frames Transmitted Register 40.8.50. GMAC Pause Frames Transmitted Register 40.8.51. GMAC 64 Byte Frames Transmitted Register 40.8.52. GMAC 65 to 127 Byte Frames Transmitted Register 40.8.53. GMAC 128 to 255 Byte Frames Transmitted Register 40.8.54. GMAC 256 to 511 Byte Frames Transmitted Register 40.8.55. GMAC 512 to 1023 Byte Frames Transmitted Register 40.8.56. GMAC 1024 to 1518 Byte Frames Transmitted Register 40.8.57. GMAC Greater Than 1518 Byte Frames Transmitted Register 40.8.58. GMAC Transmit Underruns Register 40.8.59. GMAC Single Collision Frames Register 40.8.60. GMAC Multiple Collision Frames Register 40.8.61. GMAC Excessive Collisions Register 40.8.62. GMAC Late Collisions Register 40.8.63. GMAC Deferred Transmission Frames Register 40.8.64. GMAC Carrier Sense Errors Register 40.8.65. GMAC Octets Received Low Register 40.8.66. GMAC Octets Received High Register 40.8.67. GMAC Frames Received Register 40.8.68. GMAC Broadcast Frames Received Register 40.8.69. GMAC Multicast Frames Received Register 40.8.70. GMAC Pause Frames Received Register 40.8.71. GMAC 64 Byte Frames Received Register 40.8.72. GMAC 65 to 127 Byte Frames Received Register 40.8.73. GMAC 128 to 255 Byte Frames Received Register 40.8.74. GMAC 256 to 511 Byte Frames Received Register 40.8.75. GMAC 512 to 1023 Byte Frames Received Register 40.8.76. GMAC 1024 to 1518 Byte Frames Received Register 40.8.77. GMAC 1519 to Maximum Byte Frames Received Register 40.8.78. GMAC Undersized Frames Received Register 40.8.79. GMAC Oversized Frames Received Register 40.8.80. GMAC Jabbers Received Register 40.8.81. GMAC Frame Check Sequence Errors Register 40.8.82. GMAC Length Field Frame Errors Register 40.8.83. GMAC Receive Symbol Errors Register 40.8.84. GMAC Alignment Errors Register 40.8.85. GMAC Receive Resource Errors Register 40.8.86. GMAC Receive Overruns Register 40.8.87. GMAC IP Header Checksum Errors Register 40.8.88. GMAC TCP Checksum Errors Register 40.8.89. GMAC UDP Checksum Errors Register 40.8.90. GMAC 1588 Timer Increment Sub-nanoseconds Register 40.8.91. GMAC 1588 Timer Seconds High Register 40.8.92. GMAC 1588 Timer Seconds Low Register 40.8.93. GMAC 1588 Timer Nanoseconds Register 40.8.94. GMAC 1588 Timer Adjust Register 40.8.95. GMAC 1588 Timer Increment Register 40.8.96. GMAC PTP Event Frame Transmitted Seconds Low Register 40.8.97. GMAC PTP Event Frame Transmitted Nanoseconds Register 40.8.98. GMAC PTP Event Frame Received Seconds Low Register 40.8.99. GMAC PTP Event Frame Received Nanoseconds Register 40.8.100. GMAC PTP Peer Event Frame Transmitted Seconds Low Register 40.8.101. GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 40.8.102. GMAC PTP Peer Event Frame Received Seconds Low Register 40.8.103. GMAC PTP Peer Event Frame Received Nanoseconds Register 40.8.104. GMAC Received LPI Transitions 40.8.105. GMAC Received LPI Time 40.8.106. GMAC Transmit LPI Transitions 40.8.107. GMAC Transmit LPI Time 40.8.108. GMAC Interrupt Status Register Priority Queue x 40.8.109. GMAC Transmit Buffer Queue Base Address Register Priority Queue x 40.8.110. GMAC Receive Buffer Queue Base Address Register Priority Queue x 40.8.111. GMAC Receive Buffer Size Register Priority Queue x 40.8.112. GMAC Credit-Based Shaping Control Register 40.8.113. GMAC Credit-Based Shaping IdleSlope Register for Queue A 40.8.114. GMAC Credit-Based Shaping IdleSlope Register for Queue B 40.8.115. GMAC Screening Type 1 Register x Priority Queue 40.8.116. GMAC Screening Type 2 Register x Priority Queue 40.8.117. GMAC Interrupt Enable Register Priority Queue x 40.8.118. GMAC Interrupt Disable Register Priority Queue x 40.8.119. GMAC Interrupt Mask Register Priority Queue x 40.8.120. GMAC Screening Type 2 EtherType Register x 40.8.121. GMAC Screening Type 2 Compare Word 0 Register x 40.8.122. GMAC Screening Type 2 Compare Word 1 Register x 41. USB High Speed Device Port (UDPHS) 41.1. Description 41.2. Embedded Characteristics 41.3. Block Diagram 41.4. Typical Connection 41.5. Product Dependencies 41.5.1. Power Management 41.5.2. Interrupt Sources 41.6. Functional Description 41.6.1. UTMI Transceivers Sharing 41.6.2. USB V2.0 High Speed Device Port Introduction 41.6.3. USB V2.0 High Speed Transfer Types 41.6.4. USB Transfer Event Definitions 41.6.5. USB V2.0 High Speed BUS Transactions 41.6.6. Endpoint Configuration 41.6.7. DPRAM Management 41.6.8. Transfer With DMA 41.6.9. Transfer Without DMA 41.6.10. Handling Transactions with USB V2.0 Device Peripheral 41.6.10.1. Setup Transaction 41.6.10.2. NYET 41.6.10.3. Data IN 41.6.10.4. Data OUT 41.6.10.5. STALL 41.6.11. Speed Identification 41.6.12. USB V2.0 High Speed Global Interrupt 41.6.13. Endpoint Interrupts 41.6.14. Power Modes 41.6.14.1. Controlling Device States 41.6.14.2. Not Powered State 41.6.14.3. Entering Attached State 41.6.14.4. From Powered State to Default State (Reset) 41.6.14.5. From Default State to Address State (Address Assigned) 41.6.14.6. From Address State to Configured State (Device Configured) 41.6.14.7. Entering Suspend State (Bus Activity) 41.6.14.8. Receiving a Host Resume 41.6.14.9. Sending an External Resume 41.6.15. Test Mode 41.7. Register Summary 41.7.1. UDPHS Control Register 41.7.2. UDPHS Frame Number Register 41.7.3. UDPHS Interrupt Enable Register 41.7.4. UDPHS Interrupt Status Register 41.7.5. UDPHS Clear Interrupt Register 41.7.6. UDPHS Endpoints Reset Register 41.7.7. UDPHS Test Register 41.7.8. UDPHS Endpoint Configuration Register 41.7.9. UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 41.7.10. UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 41.7.11. UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 41.7.12. UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 41.7.13. UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 41.7.14. UDPHS Endpoint Control Register (Isochronous Endpoint) 41.7.15. UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 41.7.16. UDPHS Endpoint Set Status Register (Isochronous Endpoint) 41.7.17. UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 41.7.18. UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 41.7.19. UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 41.7.20. UDPHS Endpoint Status Register (Isochronous Endpoint) 41.7.21. UDPHS DMA Channel Transfer Descriptor 41.7.22. UDPHS DMA Next Descriptor Address Register 41.7.23. UDPHS DMA Channel Address Register 41.7.24. UDPHS DMA Channel Control Register 41.7.25. UDPHS DMA Channel Status Register 42. USB Host High Speed Port (UHPHS) 42.1. Description 42.2. Embedded Characteristics 42.3. Block Diagram 42.4. Typical Connection 42.5. Product Dependencies 42.5.1. I/O Lines 42.5.2. Power Management 42.5.3. Interrupt Sources 42.6. Functional Description 42.6.1. UTMI Transceivers Sharing 42.6.2. EHCI 42.6.3. OHCI 42.6.4. HSIC 42.7. Register Summary 42.7.1. UHPHS Host Controller Capability Register 42.7.2. UHPHS Host Controller Structural Parameters Register 42.7.3. UHPHS Host Controller Capability Parameters Register 42.7.4. UHPHS USB Command Register 42.7.5. UHPHS USB Status Register 42.7.6. UHPHS USB Interrupt Enable Register 42.7.7. UHPHS USB Frame Index Register 42.7.8. UHPHS Periodic Frame List Base Address Register 42.7.9. UHPHS Asynchronous List Address Register 42.7.10. UHPHS Configure Flag Register 42.7.11. UHPHS Port Status and Control Register 42.7.12. EHCI: REG06 - AHB Error Status 42.7.13. EHCI: REG07 - AHB Master Error Address 42.7.14. EHCI: REG08 - HSIC Enable/Disable 43. Audio Class D Amplifier (CLASSD) 43.1. Description 43.2. Embedded Characteristics 43.3. Block Diagram 43.4. Pin Name List 43.5. Product Dependencies 43.5.1. I/O Lines 43.5.2. Power Management 43.5.3. Interrupt 43.6. Functional Description 43.6.1. Interpolator 43.6.1.1. Clock Configuration 43.6.1.2. CLASSD Frequency Response 43.6.2. Equalizer 43.6.3. De-emphasis Filter Frequency Response 43.6.4. Attenuator and Recommended Input Levels 43.6.5. Pulse Width Modulator (PWM) 43.6.6. Application Schematics For Use Case Examples 43.6.7. Register Write Protection 43.7. Register Summary 43.7.1. CLASSD Control Register 43.7.2. CLASSD Mode Register 43.7.3. CLASSD Interpolator Mode Register 43.7.4. CLASSD Interpolator Status Register 43.7.5. CLASSD Transmit Holding Register 43.7.6. CLASSD Interrupt Enable Register 43.7.7. CLASSD Interrupt Disable Register 43.7.8. CLASSD Interrupt Mask Register 43.7.9. CLASSD Interrupt Status Register 43.7.10. CLASSD Write Protection Mode Register 44. Inter-IC Sound Controller (I2SC) 44.1. Description 44.2. Embedded Characteristics 44.3. Block Diagram 44.4. I/O Lines Description 44.5. Product Dependencies 44.5.1. I/O Lines 44.5.2. Power Management 44.5.3. Clocks 44.5.4. DMA Controller 44.5.5. Interrupt Sources 44.6. Functional Description 44.6.1. Initialization 44.6.2. Basic Operation 44.6.3. Master, Controller and Slave Modes 44.6.4. I2S Reception and Transmission Sequence 44.6.5. Serial Clock and Word Select Generation 44.6.6. Mono 44.6.7. Holding Registers 44.6.8. DMA Controller Operation 44.6.9. Loopback Mode 44.6.10. Interrupts 44.7. I2SC Application Examples 44.8. Register Summary 44.8.1. I2SC Control Register 44.8.2. I2SC Mode Register 44.8.3. I2SC Status Register 44.8.4. I2SC Status Clear Register 44.8.5. I2SC Status Set Register 44.8.6. I2SC Interrupt Enable Register 44.8.7. I2SC Interrupt Disable Register 44.8.8. I2SC Interrupt Mask Register 44.8.9. I2SC Receiver Holding Register 44.8.10. I2SC Transmitter Holding Register 45. Synchronous Serial Controller (SSC) 45.1. Description 45.2. Embedded Characteristics 45.3. Block Diagram 45.4. Application Block Diagram 45.5. SSC Application Examples 45.6. Pin Name List 45.7. Product Dependencies 45.7.1. I/O Lines 45.7.2. Power Management 45.7.3. Interrupt 45.8. Functional Description 45.8.1. Clock Management 45.8.1.1. Clock Divider 45.8.1.2. Transmit Clock Management 45.8.1.3. Receive Clock Management 45.8.1.4. Serial Clock Ratio Considerations 45.8.2. Transmit Operations 45.8.3. Receive Operations 45.8.4. Start 45.8.5. Frame Synchronization 45.8.5.1. Frame Sync Data 45.8.5.2. Frame Sync Edge Detection 45.8.6. Receive Compare Modes 45.8.6.1. Compare Functions 45.8.7. Data Format 45.8.8. Loop Mode 45.8.9. Interrupt 45.8.10. Register Write Protection 45.9. Register Summary 45.9.1. SSC Control Register 45.9.2. SSC Clock Mode Register 45.9.3. SSC Receive Clock Mode Register 45.9.4. SSC Receive Frame Mode Register 45.9.5. SSC Transmit Clock Mode Register 45.9.6. SSC Transmit Frame Mode Register 45.9.7. SSC Receive Holding Register 45.9.8. SSC Transmit Holding Register 45.9.9. SSC Receive Synchronization Holding Register 45.9.10. SSC Transmit Synchronization Holding Register 45.9.11. SSC Receive Compare 0 Register 45.9.12. SSC Receive Compare 1 Register 45.9.13. SSC Status Register 45.9.14. SSC Interrupt Enable Register 45.9.15. SSC Interrupt Disable Register 45.9.16. SSC Interrupt Mask Register 45.9.17. SSC Write Protection Mode Register 45.9.18. SSC Write Protection Status Register 46. Two-wire Interface (TWIHS) 46.1. Description 46.2. Embedded Characteristics 46.3. List of Abbreviations 46.4. Block Diagram 46.4.1. I/O Lines Description 46.5. Product Dependencies 46.5.1. I/O Lines 46.5.2. Power Management 46.5.3. Interrupt Sources 46.6. Functional Description 46.6.1. Transfer Format 46.6.2. Modes of Operation 46.6.3. Master Mode 46.6.3.1. Definition 46.6.3.2. Programming Master Mode 46.6.3.3. Transfer Rate Clock Source 46.6.3.4. Master Transmitter Mode 46.6.3.5. Master Receiver Mode 46.6.3.6. Internal Address 46.6.3.6.1. 7-bit Slave Addressing 46.6.3.6.2. 10-bit Slave Addressing 46.6.3.7. Repeated Start 46.6.3.8. Bus Clear Command 46.6.3.9. Using the DMA Controller (DMAC) in Master Mode 46.6.3.9.1. Data Transmit with the DMA in Master Mode 46.6.3.9.2. Data Receive with the DMA in Master Mode 46.6.3.10. SMBus Mode 46.6.3.10.1. Packet Error Checking 46.6.3.10.2. Timeouts 46.6.3.11. SMBus Quick Command (Master Mode Only) 46.6.3.12. Alternative Command 46.6.3.13. Handling Errors in Alternative Command 46.6.3.14. Read/Write Flowcharts 46.6.4. Multimaster Mode 46.6.4.1. Definition 46.6.4.2. Different Multimaster Modes 46.6.4.2.1. TWIHS as Master Only 46.6.4.2.2. TWIHS as Master or Slave 46.6.5. Slave Mode 46.6.5.1. Definition 46.6.5.2. Programming Slave Mode 46.6.5.3. Receiving Data 46.6.5.3.1. Read Sequence 46.6.5.3.2. Write Sequence 46.6.5.3.3. Clock Stretching Sequence 46.6.5.3.4. General Call 46.6.5.4. Data Transfer 46.6.5.4.1. Read Operation 46.6.5.4.2. Write Operation 46.6.5.4.3. General Call 46.6.5.4.4. Clock Stretching 46.6.5.4.4.1. Clock Stretching in Read Mode 46.6.5.4.4.2. Clock Stretching in Write Mode 46.6.5.4.5. Reversal after a Repeated Start 46.6.5.4.5.1. Reversal of Read to Write 46.6.5.4.5.2. Reversal of Write to Read 46.6.5.5. Using the DMA Controller (DMAC) in Slave Mode 46.6.5.5.1. Data Transmit with the DMA in Slave Mode 46.6.5.5.2. Data Receive with the DMA in Slave Mode 46.6.5.6. SMBus Mode 46.6.5.6.1. Packet Error Checking 46.6.5.6.2. Timeouts 46.6.5.7. High-Speed Slave Mode 46.6.5.7.1. Read/Write Operation 46.6.5.7.2. Usage 46.6.5.8. Alternative Command 46.6.5.9. Asynchronous Partial Wakeup (SleepWalking) 46.6.5.10. Slave Read Write Flowcharts 46.6.6. FIFOs 46.6.6.1. Overview 46.6.6.2. Sending Data with FIFO Enabled 46.6.6.3. Receiving Data with FIFO Enabled 46.6.6.4. Sending/Receiving with FIFO Enabled in Slave Mode 46.6.6.5. Clearing/Flushing FIFOs 46.6.6.6. TXRDY and RXRDY Behavior 46.6.6.7. Single Data Mode 46.6.6.8. Multiple Data Mode 46.6.6.8.1. TXRDY and RXRDY Configuration 46.6.6.8.2. DMAC 46.6.6.9. Transmit FIFO Lock 46.6.6.10. FIFO Pointer Error 46.6.6.11. FIFO Thresholds 46.6.6.12. FIFO Flags 46.6.7. TWIHS Comparison Function on Received Character 46.6.8. Register Write Protection 46.7. Register Summary 46.7.1. TWIHS Control Register 46.7.2. TWIHS Control Register (FIFO_ENABLED) 46.7.3. TWIHS Master Mode Register 46.7.4. TWIHS Slave Mode Register 46.7.5. TWIHS Internal Address Register 46.7.6. TWIHS Clock Waveform Generator Register 46.7.7. TWIHS Status Register 46.7.8. TWIHS Status Register (FIFO_ENABLED) 46.7.9. TWIHS SMBus Timing Register 46.7.10. TWIHS Alternative Command Register 46.7.11. TWIHS Filter Register 46.7.12. TWIHS Interrupt Enable Register 46.7.13. TWIHS Interrupt Disable Register 46.7.14. TWIHS Interrupt Mask Register 46.7.15. TWIHS Receive Holding Register 46.7.16. TWIHS Receive Holding Register (FIFO Enabled) 46.7.17. TWIHS SleepWalking Matching Register 46.7.18. TWIHS Transmit Holding Register 46.7.19. TWIHS Transmit Holding Register (FIFO Enabled) 46.7.20. TWIHS FIFO Mode Register 46.7.21. TWIHS FIFO Level Register 46.7.22. TWIHS FIFO Status Register 46.7.23. TWIHS FIFO Interrupt Enable Register 46.7.24. TWIHS FIFO Interrupt Disable Register 46.7.25. TWIHS FIFO Interrupt Mask Register 46.7.26. TWIHS Write Protection Mode Register 46.7.27. TWIHS Write Protection Status Register 47. Flexible Serial Communication Controller (FLEXCOM) 47.1. Description 47.2. Embedded Characteristics 47.2.1. USART/UART Characteristics 47.2.2. SPI Characteristics 47.2.3. TWI/SMBus Characteristics 47.3. Block Diagram 47.4. I/O Lines Description 47.5. Product Dependencies 47.5.1. I/O Lines 47.5.2. Power Management 47.5.3. Interrupt Sources 47.6. Register Accesses 47.7. USART Functional Description 47.7.1. Baud Rate Generator 47.7.1.1. Baud Rate in Asynchronous Mode 47.7.1.1.1. Baud Rate Calculation Example 47.7.1.2. Fractional Baud Rate in Asynchronous Mode 47.7.1.3. Baud Rate in Synchronous Mode or SPI Mode 47.7.1.4. Baud Rate in ISO 7816 Mode 47.7.2. Receiver and Transmitter Control 47.7.3. Synchronous and Asynchronous Modes 47.7.3.1. Transmitter Operations 47.7.3.2. Manchester Encoder 47.7.3.2.1. Drift Compensation 47.7.3.3. Asynchronous Receiver 47.7.3.4. Manchester Decoder 47.7.3.5. Radio Interface: Manchester Encoded USART Application 47.7.3.6. Synchronous Receiver 47.7.3.7. Receiver Operations 47.7.3.8. Parity 47.7.3.9. Multidrop Mode 47.7.3.10. Transmitter Timeguard 47.7.3.11. Receiver Timeout 47.7.3.12. Framing Error 47.7.3.13. Transmit Break 47.7.3.14. Receive Break 47.7.3.15. Hardware Handshaking 47.7.4. ISO7816 Mode 47.7.4.1. ISO7816 Mode Overview 47.7.4.2. Protocol T = 0 47.7.4.2.1. Receive Error Counter 47.7.4.2.2. Receive NACK Inhibit 47.7.4.2.3. Transmit Character Repetition 47.7.4.2.4. Disable Successive Receive NACK 47.7.4.3. Protocol T = 1 47.7.5. IrDA Mode 47.7.5.1. IrDA Modulation 47.7.5.2. IrDA Baud Rate 47.7.5.3. IrDA Demodulator 47.7.6. RS485 Mode 47.7.7. USART Comparison Function on Received Character 47.7.8. SPI Mode 47.7.8.1. Modes of Operation 47.7.8.2. Bit Rate 47.7.8.3. Data Transfer 47.7.8.4. Receiver and Transmitter Control 47.7.8.5. Character Transmission 47.7.8.6. Character Reception 47.7.8.7. Receiver Timeout 47.7.9. LIN Mode 47.7.9.1. Modes of Operation 47.7.9.2. Baud Rate Configuration 47.7.9.3. Receiver and Transmitter Control 47.7.9.4. Character Transmission 47.7.9.5. Character Reception 47.7.9.6. Header Transmission (Master Node Configuration) 47.7.9.7. Header Reception (Slave Node Configuration) 47.7.9.8. Slave Node Synchronization 47.7.9.9. Identifier Parity 47.7.9.10. Node Action 47.7.9.11. Response Data Length 47.7.9.12. Checksum 47.7.9.13. Frame Slot Mode 47.7.9.14. LIN Errors 47.7.9.14.1. Bit Error 47.7.9.14.2. Inconsistent Synch Field Error 47.7.9.14.3. Identifier Parity Error 47.7.9.14.4. Checksum Error 47.7.9.14.5. Slave Not Responding Error 47.7.9.14.6. Synch Tolerance Error 47.7.9.14.7. Header Timeout Error 47.7.9.15. LIN Frame Handling 47.7.9.15.1. Master Node Configuration 47.7.9.15.2. Slave Node Configuration 47.7.9.16. LIN Frame Handling with the DMAC 47.7.9.16.1. Master Node Configuration 47.7.9.16.2. Slave Node Configuration 47.7.9.17. Wakeup Request 47.7.9.18. Bus Idle Timeout 47.7.10. Test Modes 47.7.10.1. Normal Mode 47.7.10.2. Automatic Echo Mode 47.7.10.3. Local Loopback Mode 47.7.10.4. Remote Loopback Mode 47.7.11. USART FIFOs 47.7.11.1. Overview 47.7.11.2. Sending Data with FIFO Enabled 47.7.11.3. Receiving Data with FIFO Enabled 47.7.11.4. Clearing/Flushing FIFOs 47.7.11.5. TXEMPTY, TXRDY and RXRDY Behavior 47.7.11.6. FIFO Single Data Access 47.7.11.6.1. DMAC 47.7.11.7. FIFO Multiple Data Access 47.7.11.7.1. TXRDY and RXRDY Configuration 47.7.11.7.2. DMAC 47.7.11.8. Transmit FIFO Lock 47.7.11.9. FIFO Pointer Error 47.7.11.10. FIFO Thresholds 47.7.11.11. FIFO Flags 47.7.12. USART Register Write Protection 47.8. SPI Functional Description 47.8.1. Modes of Operation 47.8.2. Data Transfer 47.8.3. Master Mode Operations 47.8.3.1. Master Mode Block Diagram 47.8.3.2. Master Mode Flowchart 47.8.3.3. Clock Generation 47.8.3.4. Transfer Delays 47.8.3.5. Peripheral Selection 47.8.3.6. SPI Direct Access Memory Controller (DMAC) 47.8.3.7. Peripheral Chip Select Decoding 47.8.3.8. Peripheral Deselection without DMA 47.8.3.9. Peripheral Deselection with DMA 47.8.3.10. Mode Fault Detection 47.8.4. SPI Slave Mode 47.8.5. SPI Comparison Function on Received Character 47.8.6. SPI Asynchronous and Partial Wake-up 47.8.7. SPI FIFOs 47.8.7.1. Overview 47.8.7.2. Sending Data with FIFO Enabled 47.8.7.3. Receiving Data with FIFO Enabled 47.8.7.4. Clearing/Flushing FIFOs 47.8.7.5. TXEMPTY, TDRE and RDRF Behavior 47.8.7.6. SPI Single Data Access 47.8.7.6.1. DMAC 47.8.7.7. SPI Multiple Data Access 47.8.7.7.1. TDRE and RDRF Configuration 47.8.7.7.2. DMAC 47.8.7.8. FIFO Pointer Error 47.8.7.9. FIFO Thresholds 47.8.7.10. FIFO Flags 47.8.8. SPI Register Write Protection 47.9. TWI Functional Description 47.9.1. Transfer Format 47.9.2. Modes of Operation 47.9.3. Master Mode 47.9.3.1. Definition 47.9.3.2. Programming Master Mode 47.9.3.3. Transfer Speed/Bit Rate 47.9.3.4. Master Transmitter Mode 47.9.3.5. Master Receiver Mode 47.9.3.6. Internal Address 47.9.3.6.1. 7-bit Slave Addressing 47.9.3.6.2. 10-bit Slave Addressing 47.9.3.7. Repeated Start 47.9.3.8. Bus Clear Command 47.9.3.9. SMBus Mode 47.9.3.9.1. Packet Error Checking 47.9.3.9.2. Timeouts 47.9.3.10. SMBus Quick Command (Master Mode Only) 47.9.3.11. Alternative Command 47.9.3.12. Handling Errors in Alternative Command 47.9.3.13. Read/Write Flowcharts 47.9.4. Multi-Master Mode 47.9.4.1. Definition 47.9.4.2. Different Multi-Master Modes 47.9.4.2.1. TWI as Master Only 47.9.4.2.2. TWI as Master or Slave 47.9.5. Slave Mode 47.9.5.1. Definition 47.9.5.2. Programming Slave Mode 47.9.5.3. Receiving Data 47.9.5.3.1. Read Sequence 47.9.5.3.2. Write Sequence 47.9.5.3.3. Clock Stretching Sequence 47.9.5.3.4. General Call 47.9.5.4. Data Transfer 47.9.5.4.1. Read Operation 47.9.5.4.2. Write Operation 47.9.5.4.3. General Call 47.9.5.4.4. Clock Stretching 47.9.5.4.4.1. — Clock Stretching in Read Mode 47.9.5.4.4.2. — Clock Stretching in Write Mode 47.9.5.4.5. Reversal after a Repeated Start 47.9.5.4.5.1. — Reversal of Read to Write 47.9.5.4.5.2. — Reversal of Write to Read 47.9.5.4.6. SMBus Mode 47.9.5.4.6.1. — Packet Error Checking 47.9.5.4.6.2. — Timeouts 47.9.5.5. High-Speed Slave Mode 47.9.5.5.1. Read/Write Operation 47.9.5.5.2. Usage 47.9.5.6. Alternative Command 47.9.5.7. TWI Asynchronous and Partial Wakeup 47.9.5.8. Slave Read/Write Flowcharts 47.9.6. TWI FIFOs 47.9.6.1. Overview 47.9.6.2. Sending Data with FIFO Enabled 47.9.6.3. Receiving Data with FIFO Enabled 47.9.6.4. Sending/Receiving with FIFO Enabled in Slave Mode 47.9.6.5. Clearing/Flushing FIFOs 47.9.6.6. TXRDY and RXRDY Behavior 47.9.6.7. TWI Single Data Access 47.9.6.8. TWI Multiple Data Access 47.9.6.8.1. TXRDY and RXRDY Configuration 47.9.6.8.2. DMAC 47.9.6.9. Transmit FIFO Lock 47.9.6.10. FIFO Pointer Error 47.9.6.11. FIFO Thresholds 47.9.6.12. FIFO Flags 47.9.7. TWI Comparison Function on Received Character 47.9.8. TWI Register Write Protection 47.10. Register Summary 47.10.1. FLEXCOM Mode Register 47.10.2. FLEXCOM Receive Holding Register 47.10.3. FLEXCOM Transmit Holding Register 47.10.4. USART Control Register 47.10.5. USART Control Register (SPI_MODE) 47.10.6. USART Mode Register 47.10.7. USART Mode Register (SPI_MODE) 47.10.8. USART Interrupt Enable Register 47.10.9. USART Interrupt Enable Register (SPI_MODE) 47.10.10. USART Interrupt Enable Register (LIN_MODE) 47.10.11. USART Interrupt Disable Register 47.10.12. USART Interrupt Disable Register (SPI_MODE) 47.10.13. USART Interrupt Disable Register (LIN_MODE) 47.10.14. USART Interrupt Mask Register 47.10.15. USART Interrupt Mask Register (SPI_MODE) 47.10.16. USART Interrupt Mask Register (LIN_MODE) 47.10.17. USART Channel Status Register 47.10.18. USART Channel Status Register (SPI_MODE) 47.10.19. USART Channel Status Register (LIN_MODE) 47.10.20. USART Receive Holding Register 47.10.21. USART Receive Holding Register (FIFO Multi Data) 47.10.22. USART Transmit Holding Register 47.10.23. USART Transmit Holding Register (FIFO Multi Data) 47.10.24. USART Baud Rate Generator Register 47.10.25. USART Receiver Timeout Register 47.10.26. USART Transmitter Timeguard Register 47.10.27. USART FI DI RATIO Register 47.10.28. USART Number of Errors Register 47.10.29. USART IrDA FILTER Register 47.10.30. USART Manchester Configuration Register 47.10.31. USART LIN Mode Register 47.10.32. USART LIN Identifier Register 47.10.33. USART LIN Baud Rate Register 47.10.34. USART Comparison Register 47.10.35. USART FIFO Mode Register 47.10.36. USART FIFO Level Register 47.10.37. USART FIFO Interrupt Enable Register 47.10.38. USART FIFO Interrupt Disable Register 47.10.39. USART FIFO Interrupt Mask Register 47.10.40. USART FIFO Event Status Register 47.10.41. USART Write Protection Mode Register 47.10.42. USART Write Protection Status Register 47.10.43. SPI Control Register 47.10.44. SPI Mode Register 47.10.45. SPI Receive Data Register 47.10.46. SPI Receive Data Register (FIFO Multiple Data, 8-bit) 47.10.47. SPI Receive Data Register (FIFO Multiple Data, 16-bit) 47.10.48. SPI Transmit Data Register 47.10.49. SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 47.10.50. SPI Status Register 47.10.51. SPI Interrupt Enable Register 47.10.52. SPI Interrupt Disable Register 47.10.53. SPI Interrupt Mask Register 47.10.54. SPI Chip Select Register 47.10.55. SPI FIFO Mode Register 47.10.56. SPI FIFO Level Register 47.10.57. SPI Comparison Register 47.10.58. SPI Write Protection Mode Register 47.10.59. SPI Write Protection Status Register 47.10.60. TWI Control Register 47.10.61. TWI Control Register (FIFO_ENABLED) 47.10.62. TWI Master Mode Register 47.10.63. TWI Slave Mode Register 47.10.64. TWI Internal Address Register 47.10.65. TWI Clock Waveform Generator Register 47.10.66. TWI Status Register 47.10.67. TWI Status Register (FIFO ENABLED) 47.10.68. TWI Interrupt Enable Register 47.10.69. TWI Interrupt Disable Register 47.10.70. TWI Interrupt Mask Register 47.10.71. TWI Receive Holding Register 47.10.72. TWI Receive Holding Register (FIFO Enabled) 47.10.73. TWI Transmit Holding Register 47.10.74. TWI Transmit Holding Register (FIFO Enabled) 47.10.75. TWI SMBus Timing Register 47.10.76. TWI Alternative Command Register 47.10.77. TWI Filter Register 47.10.78. TWI Matching Register 47.10.79. TWI FIFO Mode Register 47.10.80. TWI FIFO Level Register 47.10.81. TWI FIFO Status Register 47.10.82. TWI FIFO Interrupt Enable Register 47.10.83. TWI FIFO Interrupt Disable Register 47.10.84. TWI FIFO Interrupt Mask Register 47.10.85. TWI Write Protection Mode Register 47.10.86. TWI Write Protection Status Register 48. Universal Asynchronous Receiver Transmitter (UART) 48.1. Description 48.2. Embedded Characteristics 48.3. Block Diagram 48.4. Product Dependencies 48.4.1. I/O Lines 48.4.2. Power Management 48.4.3. Interrupt Sources 48.5. Functional Description 48.5.1. Baud Rate Generator 48.5.2. Receiver 48.5.2.1. Receiver Reset, Enable and Disable 48.5.2.2. Start Detection and Data Sampling 48.5.2.3. Receiver Ready 48.5.2.4. Receiver Overrun 48.5.2.5. Parity Error 48.5.2.6. Receiver Framing Error 48.5.2.7. Receiver Digital Filter 48.5.2.8. Receiver Time-out 48.5.3. Transmitter 48.5.3.1. Transmitter Reset, Enable and Disable 48.5.3.2. Transmit Format 48.5.3.3. Transmitter Control 48.5.4. DMA Support 48.5.5. Comparison Function on Received Character 48.5.6. Asynchronous and Partial Wake-Up 48.5.7. Register Write Protection 48.5.8. Test Modes 48.6. Register Summary 48.6.1. UART Control Register 48.6.2. UART Mode Register 48.6.3. UART Interrupt Enable Register 48.6.4. UART Interrupt Disable Register 48.6.5. UART Interrupt Mask Register 48.6.6. UART Interrupt Status Register 48.6.7. UART Receiver Holding Register 48.6.8. UART Transmit Holding Register 48.6.9. UART Baud Rate Generator Register 48.6.10. UART Comparison Register 48.6.11. UART Receiver Time-out Register 48.6.12. UART Write Protection Mode Register 49. Serial Peripheral Interface (SPI) 49.1. Description 49.2. Embedded Characteristics 49.3. Block Diagram 49.4. Application Block Diagram 49.5. Signal Description 49.6. Product Dependencies 49.6.1. I/O Lines 49.6.2. Power Management 49.6.3. Interrupt 49.6.4. Direct Memory Access Controller (DMAC) 49.7. Functional Description 49.7.1. Modes of Operation 49.7.2. Data Transfer 49.7.3. Master Mode Operations 49.7.3.1. Master Mode Block Diagram 49.7.3.2. Master Mode Flow Diagram 49.7.3.3. Clock Generation 49.7.3.4. Transfer Delays 49.7.3.5. Peripheral Selection 49.7.3.6. SPI Direct Access Memory Controller (DMAC) 49.7.3.7. Peripheral Chip Select Decoding 49.7.3.8. Peripheral Deselection without DMA 49.7.3.9. Peripheral Deselection with DMA 49.7.3.10. Mode Fault Detection 49.7.4. SPI Slave Mode 49.7.5. SPI Comparison Function on Received Character 49.7.6. SPI Asynchronous and Partial Wakeup (SleepWalking) 49.7.7. FIFOs 49.7.7.1. Overview 49.7.7.2. Sending Data with FIFO Enabled 49.7.7.3. Receiving Data with FIFO Enabled 49.7.7.4. Clearing/Flushing FIFOs 49.7.7.5. TXEMPTY, TDRE and RDRF Behavior 49.7.7.6. Single Data Mode 49.7.7.6.1. DMAC 49.7.7.7. Multiple Data Mode 49.7.7.7.1. TDRE and RDRF Configuration 49.7.7.7.2. DMAC 49.7.7.8. FIFO Pointer Error 49.7.7.9. FIFO Thresholds 49.7.7.10. FIFO Flags 49.7.8. Register Write Protection 49.8. Register Summary 49.8.1. SPI Control Register 49.8.2. SPI Mode Register 49.8.3. SPI Receive Data Register 49.8.4. SPI Receive Data Register (FIFO Multiple Data, 8-bit) 49.8.5. SPI Receive Data Register (FIFO Multiple Data, 16-bit) 49.8.6. SPI Transmit Data Register 49.8.7. SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 49.8.8. SPI Status Register 49.8.9. SPI Interrupt Enable Register 49.8.10. SPI Interrupt Disable Register 49.8.11. SPI Interrupt Mask Register 49.8.12. SPI Chip Select Register 49.8.13. SPI FIFO Mode Register 49.8.14. SPI FIFO Level Register 49.8.15. SPI Comparison Register 49.8.16. SPI Write Protection Mode Register 49.8.17. SPI Write Protection Status Register 50. Quad Serial Peripheral Interface (QSPI) 50.1. Description 50.2. Embedded Characteristics 50.3. Block Diagram 50.4. Signal Description 50.5. Product Dependencies 50.5.1. I/O Lines 50.5.2. Power Management 50.5.3. Interrupt Sources 50.5.4. Direct Memory Access Controller (DMA) 50.6. Functional Description 50.6.1. Serial Clock Baud Rate 50.6.2. Serial Clock Phase and Polarity 50.6.3. Transfer Delays 50.6.4. QSPI SPI Mode 50.6.4.1. SPI Mode Operations 50.6.4.2. SPI Mode Block Diagram 50.6.4.3. SPI Mode Flow Diagram 50.6.4.4. Peripheral Deselection without DMA 50.6.4.5. Peripheral Deselection with DMA 50.6.5. QSPI Serial Memory Mode 50.6.5.1. Instruction Frame 50.6.5.2. Instruction Frame Transmission 50.6.5.3. Read Memory Transfer 50.6.5.4. Continuous Read Mode 50.6.5.5. Instruction Frame Transmission Examples 50.6.6. Scrambling/Unscrambling Function 50.6.6.1. Clearing Scrambling Keys On Embedded Flash Erase 50.6.7. Register Write Protection 50.7. Register Summary 50.7.1. QSPI Control Register 50.7.2. QSPI Mode Register 50.7.3. QSPI Receive Data Register 50.7.4. QSPI Transmit Data Register 50.7.5. QSPI Status Register 50.7.6. QSPI Interrupt Enable Register 50.7.7. QSPI Interrupt Disable Register 50.7.8. QSPI Interrupt Mask Register 50.7.9. QSPI Serial Clock Register 50.7.10. QSPI Instruction Address Register 50.7.11. QSPI Instruction Code Register 50.7.12. QSPI Instruction Frame Register 50.7.13. QSPI Scrambling Mode Register 50.7.14. QSPI Scrambling Key Register 50.7.15. QSPI Write Protection Mode Register 50.7.16. QSPI Write Protection Status Register 51. Secure Digital MultiMedia Card Controller (SDMMC) 51.1. Description 51.2. Embedded Characteristics 51.3. Reference Documents 51.4. Block Diagram 51.5. Application Block Diagram 51.6. Pin Name List 51.7. Product Dependencies 51.7.1. I/O Lines 51.7.2. Power Management 51.7.3. Interrupt Sources 51.8. SD/SDIO Operating Mode 51.9. e.MMC Operating Mode 51.9.1. Boot Operation Mode 51.9.1.1. Boot Procedure, Processor Mode 51.9.1.2. Boot Procedure, SDMA Mode 51.9.1.3. Boot Procedure, ADMA Mode 51.10. SDR104 / HS200 Tuning 51.10.1. DLL and Sampling Point 51.10.2. Retuning Method 51.10.2.1. SDMMC Tuning Sequence 51.11. I/O Calibration 51.12. Register Summary 51.12.1. SDMMC SDMA System Address / Argument 2 Register 51.12.2. SDMMC Block Size Register 51.12.3. SDMMC Block Count Register 51.12.4. SDMMC Argument 1 Register 51.12.5. SDMMC Transfer Mode Register 51.12.6. SDMMC Command Register 51.12.7. SDMMC Response Register x 51.12.8. SDMMC Buffer Data Port Register 51.12.9. SDMMC Present State Register 51.12.10. SDMMC Host Control 1 Register (SD_SDIO) 51.12.11. SDMMC Host Control 1 Register (e.MMC) 51.12.12. SDMMC Power Control Register 51.12.13. SDMMC Block Gap Control Register (SD_SDIO) 51.12.14. SDMMC Block Gap Control Register (e.MMC) 51.12.15. SDMMC Wakeup Control Register (SD_SDIO) 51.12.16. SDMMC Clock Control Register 51.12.17. SDMMC Timeout Control Register 51.12.18. SDMMC Software Reset Register 51.12.19. SDMMC Normal Interrupt Status Register (SD_SDIO) 51.12.20. SDMMC Normal Interrupt Status Register (e.MMC) 51.12.21. SDMMC Error Interrupt Status Register (SD_SDIO) 51.12.22. SDMMC Error Interrupt Status Register (e.MMC) 51.12.23. SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 51.12.24. SDMMC Normal Interrupt Status Enable Register (e.MMC) 51.12.25. SDMMC Error Interrupt Status Enable Register (SD_SDIO) 51.12.26. SDMMC Error Interrupt Status Enable Register (e.MMC) 51.12.27. SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 51.12.28. SDMMC Normal Interrupt Signal Enable Register (e.MMC) 51.12.29. SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 51.12.30. SDMMC Error Interrupt Signal Enable Register (e.MMC) 51.12.31. SDMMC Auto CMD Error Status Register 51.12.32. SDMMC Host Control 2 Register (SD_SDIO) 51.12.33. SDMMC Host Control 2 Register (e.MMC) 51.12.34. SDMMC Capabilities 0 Register 51.12.35. SDMMC Capabilities 1 Register 51.12.36. SDMMC Maximum Current Capabilities Register 51.12.37. SDMMC Force Event Register for Auto CMD Error Status 51.12.38. SDMMC Force Event Register for Error Interrupt Status 51.12.39. SDMMC ADMA Error Status Register 51.12.40. SDMMC ADMA System Address Register 0 51.12.41. SDMMC Preset Value Register 51.12.42. SDMMC Slot Interrupt Status Register 51.12.43. SDMMC Host Controller Version Register 51.12.44. SDMMC Additional Present State Register 51.12.45. SDMMC e.MMC Control 1 Register 51.12.46. SDMMC e.MMC Control 2 Register 51.12.47. SDMMC AHB Control Register 51.12.48. SDMMC Clock Control 2 Register 51.12.49. SDMMC Retuning Control 1 Register 51.12.50. SDMMC Retuning Control 2 Register 51.12.51. SDMMC Retuning Counter Value Register 51.12.52. SDMMC Retuning Interrupt Status Enable Register 51.12.53. SDMMC Retuning Interrupt Signal Enable Register 51.12.54. SDMMC Retuning Interrupt Status Register 51.12.55. SDMMC Retuning Status Slots Register 51.12.56. SDMMC Tuning Control Register 51.12.57. SDMMC Capabilities Control Register 51.12.58. SDMMC Calibration Control Register 52. Image Sensor Controller (ISC) 52.1. Description 52.2. Embedded Characteristics 52.3. Block Diagram and Use Cases 52.3.1. Image Sensor Controller Functional Diagrams 52.4. I/O Lines Description 52.4.1. Image Sensor Controller Clock Domain Diagram 52.4.2. Image Sensor Controller Typical Use Cases 52.5. Product Dependencies 52.5.1. I/O Lines 52.5.2. Power Management 52.5.3. Interrupt Sources 52.6. Functional Description 52.6.1. ISC Clock Management 52.6.1.1. Software Requirement 52.6.2. Parallel Interface Timing Description 52.6.3. BT.601/656/1120 Embedded Timing Synchronization Operation 52.6.4. Parallel Interface External Sensor Connections 52.6.4.1. YCbCr, 10-bit CCIR656 with Embedded Synchronization 52.6.4.2. YCbCr, 8-bit CCIR656 with Embedded Synchronization 52.6.4.3. Raw Bayer Parallel Interface 52.6.4.4. Monochrome Parallel Interface 52.6.5. Parallel Front End (PFE) Module 52.6.5.1. Update the ISC Profile 52.6.5.2. Software Requirements 52.6.6. White Balance (WB) Module 52.6.7. Color Filter Array (CFA) Interpolation Module 52.6.7.1. Frame Size Requirement when Edge Interpolation is Off, ISC_CFA_CFG.EITPOL Cleared 52.6.7.2. Frame Size Requirement when Edge Interpolation is On, ISC_CFA_CFG.EITPOL Set 52.6.7.3. Bayer Mode and Edge Interpolation Description 52.6.8. Color Correction (CC) Module 52.6.9. Gamma Curve (GAM) Module 52.6.10. Color Space Conversion (CSC) Module 52.6.11. Contrast, Brightness, Hue and Saturation 52.6.12. 4:4:4 To 4:2:2 Chrominance Horizontal Subsampler (SUB422) Module 52.6.13. 4:2:2 To 4:2:0 Chrominance Vertical Subsampler (SUB420) Module 52.6.14. Rounding, Limiting and Packing (RLP) Module 52.6.15. DMA Interface 52.6.15.1. Descriptor Memory Address Mapping 52.6.15.2. Descriptor Memory Mapping 52.6.15.3. Example: Memory Mapping for 16-bit Packed, DMA Interface IMODE = 1 at ISC_DAD0.AD0 Location 52.6.15.4. Example: Memory Mapping for 12-bit YC420SP, DMA Interface IMODE = 5 52.6.15.5. Example: Memory Mapping for 12-bit YC420P, DMA Interface IMODE = 6 52.6.16. Histogram Module 52.7. Register Summary 52.7.1. ISC Control Enable Register 0 52.7.2. ISC Control Disable Register 0 52.7.3. ISC Control Status Register 0 52.7.4. ISC Parallel Front End Configuration 0 Register 52.7.5. ISC Parallel Front End Configuration 1 Register 52.7.6. ISC Parallel Front End Configuration 2 Register 52.7.7. ISC Clock Enable Register 52.7.8. ISC Clock Disable Register 52.7.9. ISC Clock Status Register 52.7.10. ISC Clock Configuration Register 52.7.11. ISC Interrupt Enable Register 52.7.12. ISC Interrupt Disable Register 52.7.13. ISC Interrupt Mask Register 52.7.14. ISC Interrupt Status Register 52.7.15. ISC White Balance Control Register 52.7.16. ISC White Balance Configuration Register 52.7.17. ISC White Balance Offset for R, GR Register 52.7.18. ISC White Balance Offset for B and GB Register 52.7.19. ISC White Balance Gain for R, GR Register 52.7.20. ISC White Balance Gain for B, GB Register 52.7.21. ISC Color Filter Array Control Register 52.7.22. ISC Color Filter Array Configuration Register 52.7.23. ISC Color Correction Control Register 52.7.24. ISC Color Correction RR RG Register 52.7.25. ISC Color Correction RB OR Register 52.7.26. ISC Color Correction GR GG Register 52.7.27. ISC Color Correction GB OG Register 52.7.28. ISC Color Correction BR BG Register 52.7.29. ISC Color Correction BB OB Register 52.7.30. ISC Gamma Correction Control Register 52.7.31. ISC Gamma Correction Blue Entry Register x [x=0..63] 52.7.32. ISC Gamma Correction Green Entry Register x [x=0..63] 52.7.33. ISC Gamma Correction Red Entry Register x [x=0..63] 52.7.34. ISC Color Space Conversion Control Register 52.7.35. ISC Color Space Conversion YR YG Register 52.7.36. ISC Color Space Conversion YB OY Register 52.7.37. ISC Color Space Conversion CBR CBG Register 52.7.38. ISC Color Space Conversion CBB OCB Register 52.7.39. ISC Color Space Conversion CRR CRG Register 52.7.40. ISC Color Space Conversion CRB OCR Register 52.7.41. ISC Contrast And Brightness Control Register 52.7.42. ISC Contrast And Brightness Configuration Register 52.7.43. ISC Contrast And Brightness, Brightness Register 52.7.44. ISC Contrast And Brightness, Contrast Register 52.7.45. ISC Subsampling 4:4:4 to 4:2:2 Control Register 52.7.46. ISC Subsampling 4:4:4 to 4:2:2 Configuration Register 52.7.47. ISC Subsampling 4:2:2 to 4:2:0 Control Register 52.7.48. ISC Rounding, Limiting and Packing Configuration Register 52.7.49. ISC Histogram Control Register 52.7.50. ISC Histogram Configuration Register 52.7.51. ISC DMA Configuration Register 52.7.52. ISC DMA Control Register 52.7.53. ISC DMA Descriptor Address Register 52.7.54. ISC DMA Address 0 Register 52.7.55. ISC DMA Stride 0 Register 52.7.56. ISC DMA Address 1 Register 52.7.57. ISC DMA Stride 1 Register 52.7.58. ISC DMA Address 2 Register 52.7.59. ISC DMA Stride 2 Register 52.7.60. ISC Histogram Entry x [x=0..511] 53. Controller Area Network (MCAN) 53.1. Description 53.2. Embedded Characteristics 53.3. Block Diagram 53.4. Product Dependencies 53.4.1. I/O Lines 53.4.2. Power Management 53.4.3. Interrupt Sources 53.4.4. Address Configuration 53.5. Functional Description 53.5.1. Operating Modes 53.5.1.1. Software Initialization 53.5.1.2. Normal Operation 53.5.1.3. CAN FD Operation 53.5.1.4. Transmitter Delay Compensation 53.5.1.4.1. Description 53.5.1.4.2. Transmitter Delay Measurement 53.5.1.5. Restricted Operation Mode 53.5.1.6. Bus Monitoring Mode 53.5.1.7. Disabled Automatic Retransmission 53.5.1.7.1. Frame Transmission in DAR Mode 53.5.1.8. Power-down (Sleep Mode) 53.5.1.9. Test Modes 53.5.1.9.1. External Loop Back Mode 53.5.1.9.2. Internal Loop Back Mode 53.5.2. Timestamp Generation 53.5.3. Timeout Counter 53.5.4. Rx Handling 53.5.4.1. Acceptance Filtering 53.5.4.1.1. Range Filter 53.5.4.1.2. Filter for Specific IDs 53.5.4.1.3. Classic Bit Mask Filter 53.5.4.1.4. Standard Message ID Filtering 53.5.4.1.4.1. Extended Message ID Filtering 53.5.4.2. Rx FIFOs 53.5.4.2.1. Rx FIFO Blocking Mode 53.5.4.2.2. Rx FIFO Overwrite Mode 53.5.4.3. Dedicated Rx Buffers 53.5.4.3.1. Rx Buffer Handling 53.5.4.4. Debug on CAN Support 53.5.4.4.1. Filtering for Debug Messages 53.5.4.4.2. Debug Message Handling 53.5.5. Tx Handling 53.5.5.1. Transmit Pause 53.5.5.2. Dedicated Tx Buffers 53.5.5.3. Tx FIFO 53.5.5.4. Tx Queue 53.5.5.5. Mixed Dedicated Tx Buffers / Tx FIFO 53.5.5.6. Mixed Dedicated Tx Buffers / Tx Queue 53.5.5.7. Transmit Cancellation 53.5.5.8. Tx Event Handling 53.5.6. FIFO Acknowledge Handling 53.5.7. Message RAM 53.5.7.1. Message RAM Configuration 53.5.7.2. Rx Buffer and FIFO Element 53.5.7.3. Tx Buffer Element 53.5.7.4. Tx Event FIFO Element 53.5.7.5. Standard Message ID Filter Element 53.5.7.6. Extended Message ID Filter Element 53.5.8. Hardware Reset Description 53.5.9. Access to Reserved Register Addresses 53.6. Register Summary 53.6.1. MCAN Endian Register 53.6.2. MCAN Customer Register 53.6.3. MCAN Data Bit Timing and Prescaler Register 53.6.4. MCAN Test Register 53.6.5. MCAN RAM Watchdog Register 53.6.6. MCAN CC Control Register 53.6.7. MCAN Nominal Bit Timing and Prescaler Register 53.6.8. MCAN Timestamp Counter Configuration Register 53.6.9. MCAN Timestamp Counter Value Register 53.6.10. MCAN Timeout Counter Configuration Register 53.6.11. MCAN Timeout Counter Value Register 53.6.12. MCAN Error Counter Register 53.6.13. MCAN Protocol Status Register 53.6.14. MCAN Transmitter Delay Compensation Register 53.6.15. MCAN Interrupt Register 53.6.16. MCAN Interrupt Enable Register 53.6.17. MCAN Interrupt Line Select Register 53.6.18. MCAN Interrupt Line Enable 53.6.19. MCAN Global Filter Configuration 53.6.20. MCAN Standard ID Filter Configuration 53.6.21. MCAN Extended ID Filter Configuration 53.6.22. MCAN Extended ID AND Mask 53.6.23. MCAN High Priority Message Status 53.6.24. MCAN New Data 1 53.6.25. MCAN New Data 2 53.6.26. MCAN Receive FIFO 0 Configuration 53.6.27. MCAN Receive FIFO 0 Status 53.6.28. MCAN Receive FIFO 0 Acknowledge 53.6.29. MCAN Receive Buffer Configuration 53.6.30. MCAN Receive FIFO 1 Configuration 53.6.31. MCAN Receive FIFO 1 Status 53.6.32. MCAN Receive FIFO 1 Acknowledge 53.6.33. MCAN Receive Buffer / FIFO Element Size Configuration 53.6.34. MCAN Tx Buffer Configuration 53.6.35. MCAN Tx FIFO/Queue Status 53.6.36. MCAN Tx Buffer Element Size Configuration 53.6.37. MCAN Transmit Buffer Request Pending 53.6.38. MCAN Transmit Buffer Add Request 53.6.39. MCAN Transmit Buffer Cancellation Request 53.6.40. MCAN Transmit Buffer Transmission Occurred 53.6.41. MCAN Transmit Buffer Cancellation Finished 53.6.42. MCAN Transmit Buffer Transmission Interrupt Enable 53.6.43. MCAN Transmit Buffer Cancellation Finished Interrupt Enable 53.6.44. MCAN Transmit Event FIFO Configuration 53.6.45. MCAN Tx Event FIFO Status 53.6.46. MCAN Tx Event FIFO Acknowledge 54. Timer Counter (TC) 54.1. Description 54.2. Embedded Characteristics 54.3. Block Diagram 54.4. Pin List 54.5. Product Dependencies 54.5.1. I/O Lines 54.5.2. Power Management 54.5.3. Interrupt Sources 54.5.4. Synchronization Inputs from PWM 54.5.5. Fault Output 54.6. Functional Description 54.6.1. Description 54.6.2. 32-bit Counter 54.6.3. Clock Selection 54.6.4. Clock Control 54.6.5. Operating Modes 54.6.6. Trigger 54.6.7. Capture Mode 54.6.8. Capture Registers A and B 54.6.9. Transfer with DMAC in Capture Mode 54.6.10. Trigger Conditions 54.6.11. Waveform Mode 54.6.12. Waveform Selection 54.6.12.1. WAVSEL = 00 54.6.12.2. WAVSEL = 10 54.6.12.3. WAVSEL = 01 54.6.12.4. WAVSEL = 11 54.6.13. External Event/Trigger Conditions 54.6.14. Synchronization with PWM 54.6.15. Output Controller 54.6.16. Quadrature Decoder 54.6.16.1. Description 54.6.16.2. Input Preprocessing 54.6.16.3. Direction Status and Change Detection 54.6.16.4. Position and Rotation Measurement 54.6.16.5. Speed Measurement 54.6.16.6. Detecting a Missing Index Pulse 54.6.16.7. Detecting Contamination/Dust at Rotary Encoder Low Speed 54.6.16.8. Missing Pulse Detection and Autocorrection 54.6.17. 2-bit Gray Up/Down Counter for Stepper Motor 54.6.18. Fault Mode 54.6.19. Register Write Protection 54.7. Register Summary 54.7.1. TC Channel Control Register 54.7.2. TC Channel Mode Register: Capture Mode 54.7.3. TC Channel Mode Register: Waveform Mode 54.7.4. TC Stepper Motor Mode Register 54.7.5. TC Register AB 54.7.6. TC Counter Value Register 54.7.7. TC Register A 54.7.8. TC Register B 54.7.9. TC Register C 54.7.10. TC Interrupt Status Register 54.7.11. TC Interrupt Enable Register 54.7.12. TC Interrupt Disable Register 54.7.13. TC Interrupt Mask Register 54.7.14. TC Extended Mode Register 54.7.15. TC Block Control Register 54.7.16. TC Block Mode Register 54.7.17. TC QDEC Interrupt Enable Register 54.7.18. TC QDEC Interrupt Disable Register 54.7.19. TC QDEC Interrupt Mask Register 54.7.20. TC QDEC Interrupt Status Register 54.7.21. TC Fault Mode Register 54.7.22. TC Write Protection Mode Register 55. Pulse Density Modulation Interface Controller (PDMIC) 55.1. Description 55.2. Embedded Characteristics 55.3. Block Diagram 55.4. Signal Description 55.5. Product Dependencies 55.5.1. I/O Lines 55.5.2. Power Management 55.5.3. Interrupt Sources 55.6. Functional Description 55.6.1. PDM Interface 55.6.1.1. Description 55.6.1.2. Start-up Sequence 55.6.2. Digital Signal Processing (Digital Filter) 55.6.2.1. Description 55.6.2.2. Decimation Filter 55.6.2.3. Droop Compensation 55.6.2.4. Low Pass Filter 55.6.2.5. High Pass Filter 55.6.2.6. Gain and Offset Compensation 55.6.3. Conversion Results 55.6.4. Register Write Protection 55.7. Register Summary 55.7.1. PDMIC Control Register 55.7.2. PDMIC Mode Register 55.7.3. PDMIC Converted Data Register 55.7.4. PDMIC Interrupt Enable Register 55.7.5. PDMIC Interrupt Disable Register 55.7.6. PDMIC Interrupt Mask Register 55.7.7. PDMIC Interrupt Status Register 55.7.8. PDMIC DSP Configuration Register 0 55.7.9. PDMIC DSP Configuration Register 1 55.7.10. PDMIC Write Protection Mode Register 55.7.11. PDMIC Write Protection Status Register 56. Pulse Width Modulation Controller (PWM) 56.1. Description 56.2. Embedded Characteristics 56.3. Block Diagram 56.4. I/O Lines Description 56.5. Product Dependencies 56.5.1. I/O Lines 56.5.2. Power Management 56.5.3. Interrupt Sources 56.5.4. Fault Inputs 56.5.5. External Trigger Inputs 56.6. Functional Description 56.6.1. PWM Clock Generator 56.6.2. PWM Channel 56.6.2.1. Channel Block Diagram 56.6.2.2. Comparator 56.6.2.3. Trigger Selection for Timer Counter 56.6.2.3.1. Delay Measurement 56.6.2.3.2. Cumulated ON Time Measurement 56.6.2.4. 2-bit Gray Up/Down Counter for Stepper Motor 56.6.2.5. Dead-Time Generator 56.6.2.5.1. PWM Push-Pull Mode 56.6.2.6. Output Override 56.6.2.7. Fault Protection 56.6.2.7.1. Recoverable Fault 56.6.2.8. Spread Spectrum Counter 56.6.2.9. Synchronous Channels 56.6.2.9.1. Method 1: Manual write of duty-cycle values and manual trigger of the update 56.6.2.9.2. Method 2: Manual write of duty-cycle values and automatic trigger of the update 56.6.2.9.3. Method 3: Automatic write of duty-cycle values and automatic trigger of the update 56.6.2.10. Update Time for Double-Buffering Registers 56.6.3. PWM Comparison Units 56.6.4. PWM Event Lines 56.6.5. PWM External Trigger Mode 56.6.5.1. External PWM Reset Mode 56.6.5.1.1. Application Example 56.6.5.2. External PWM Start Mode 56.6.5.2.1. Application Example 56.6.5.3. Cycle-By-Cycle Duty Mode 56.6.5.3.1. Application Example 56.6.5.4. Leading-Edge Blanking (LEB) 56.6.6. PWM Controller Operations 56.6.6.1. Initialization 56.6.6.2. Source Clock Selection Criteria 56.6.6.3. Changing the Duty-Cycle, the Period and the Dead-Times 56.6.6.4. Changing the Update Period of Synchronous Channels 56.6.6.5. Changing the Comparison Value and the Comparison Configuration 56.6.6.6. Interrupt Sources 56.6.7. Register Write Protection 56.7. Register Summary 56.7.1. PWM Clock Register 56.7.2. PWM Enable Register 56.7.3. PWM Disable Register 56.7.4. PWM Status Register 56.7.5. PWM Interrupt Enable Register 1 56.7.6. PWM Interrupt Disable Register 1 56.7.7. PWM Interrupt Mask Register 1 56.7.8. PWM Interrupt Status Register 1 56.7.9. PWM Sync Channels Mode Register 56.7.10. PWM DMA Register 56.7.11. PWM Sync Channels Update Control Register 56.7.12. PWM Sync Channels Update Period Register 56.7.13. PWM Sync Channels Update Period Update Register 56.7.14. PWM Interrupt Enable Register 2 56.7.15. PWM Interrupt Disable Register 2 56.7.16. PWM Interrupt Mask Register 2 56.7.17. PWM Interrupt Status Register 2 56.7.18. PWM Output Override Value Register 56.7.19. PWM Output Selection Register 56.7.20. PWM Output Selection Set Register 56.7.21. PWM Output Selection Clear Register 56.7.22. PWM Output Selection Set Update Register 56.7.23. PWM Output Selection Clear Update Register 56.7.24. PWM Fault Mode Register 56.7.25. PWM Fault Status Register 56.7.26. PWM Fault Clear Register 56.7.27. PWM Fault Protection Value Register 1 56.7.28. PWM Fault Protection Enable Register 56.7.29. PWM Event Line x Mode Register 56.7.30. PWM Spread Spectrum Register 56.7.31. PWM Spread Spectrum Update Register 56.7.32. PWM Stepper Motor Mode Register 56.7.33. PWM Fault Protection Value Register 2 56.7.34. PWM Write Protection Control Register 56.7.35. PWM Write Protection Status Register 56.7.36. PWM Comparison x Value Register 56.7.37. PWM Comparison x Value Update Register 56.7.38. PWM Comparison x Mode Register 56.7.39. PWM Comparison x Mode Update Register 56.7.40. PWM Channel Mode Register 56.7.41. PWM Channel Duty Cycle Register 56.7.42. PWM Channel Duty Cycle Update Register 56.7.43. PWM Channel Period Register 56.7.44. PWM Channel Period Update Register 56.7.45. PWM Channel Counter Register 56.7.46. PWM Channel Dead Time Register 56.7.47. PWM Channel Dead Time Update Register 56.7.48. PWM Channel Mode Update Register 56.7.49. PWM External Trigger Register 56.7.50. PWM Leading-Edge Blanking Register 57. Secure Fuse Controller (SFC) 57.1. Description 57.2. Embedded Characteristics 57.3. Block Diagram 57.4. Functional Description 57.4.1. Accessing the SFC 57.4.2. Fuse Partitioning 57.4.3. Fuse Integrity Checking 57.4.4. Fuse Integrity Live Checking 57.4.5. Fuse Access 57.4.5.1. Fuse Reading 57.4.5.2. Fuse Programming 57.4.5.3. Fuse Masking 57.4.6. Fuse Functions 57.5. Register Summary 57.5.1. SFC Key Register 57.5.2. SFC Mode Register 57.5.3. SFC Interrupt Enable Register 57.5.4. SFC Interrupt Disable Register 57.5.5. SFC Interrupt Mask Register 57.5.6. SFC Status Register 57.5.7. SFC Data Register x 58. Integrity Check Monitor (ICM) 58.1. Description 58.2. Embedded Characteristics 58.3. Block Diagram 58.4. Product Dependencies 58.4.1. Power Management 58.4.2. Interrupt Sources 58.5. Functional Description 58.5.1. Overview 58.5.2. ICM Region Descriptor Structure 58.5.2.1. ICM Region Start Address Structure Member 58.5.2.2. ICM Region Configuration Structure Member 58.5.2.3. ICM Region Control Structure Member 58.5.2.4. ICM Region Next Address Structure Member 58.5.3. ICM Hash Area 58.5.3.1. Message Digest Example 58.5.4. Using ICM as SHA Engine 58.5.4.1. Settings for Simple SHA Calculation 58.5.4.2. Processing Period 58.5.5. ICM Automatic Monitoring Mode 58.5.6. Programming the ICM 58.5.7. Security Features 58.6. Register Summary 58.6.1. ICM Configuration Register 58.6.2. ICM Control Register 58.6.3. ICM Status Register 58.6.4. ICM Interrupt Enable Register 58.6.5. ICM Interrupt Disable Register 58.6.6. ICM Interrupt Mask Register 58.6.7. ICM Interrupt Status Register 58.6.8. ICM Undefined Access Status Register 58.6.9. ICM Descriptor Area Start Address Register 58.6.10. ICM Hash Area Start Address Register 58.6.11. ICM User Initial Hash Value Register 59. Advanced Encryption Standard Bridge (AESB) 59.1. Description 59.2. Embedded Characteristics 59.3. Product Dependencies 59.3.1. Power Management 59.3.2. Interrupt 59.4. Functional Description 59.4.1. Operating Modes 59.4.2. Double Input Buffer 59.4.3. Start Modes 59.4.3.1. Manual Mode 59.4.3.2. Auto Mode 59.4.4. Last Output Data Mode 59.4.5. Manual and Auto Modes 59.4.5.1. If AESB_MR.LOD = 0 59.4.5.2. If AESB_MR.LOD = 1 59.4.6. Automatic Bridge Mode 59.4.6.1. Description 59.4.6.2. Configuration 59.4.7. Security Features 59.4.7.1. Unspecified Register Access Detection 59.5. Register Summary 59.5.1. AESB Control Register 59.5.2. AESB Mode Register 59.5.3. AESB Interrupt Enable Register 59.5.4. AESB Interrupt Disable Register 59.5.5. AESB Interrupt Mask Register 59.5.6. AESB Interrupt Status Register 59.5.7. AESB Key Word Register x 59.5.8. AESB Input Data Register x 59.5.9. AESB Output Data Register x 59.5.10. AESB Initialization Vector Register x 60. Advanced Encryption Standard (AES) 60.1. Description 60.2. Embedded Characteristics 60.3. Product Dependencies 60.3.1. Power Management 60.3.2. Interrupt Sources 60.4. Functional Description 60.4.1. AES Register Endianness 60.4.2. Operating Modes 60.4.3. Last Output Data Mode (CBC-MAC) 60.4.3.1. Manual and Auto Modes 60.4.3.1.1. If AES_MR.LOD = 0 60.4.3.1.2. If AES_MR.LOD = 1 60.4.3.2. DMA Mode 60.4.3.2.1. If AES_MR.LOD = 0 60.4.3.2.2. If AES_MR.LOD = 1 60.4.4. Galois/Counter Mode (GCM) 60.4.4.1. Description 60.4.4.2. Key Writing and Automatic Hash Subkey Calculation 60.4.4.3. GCM Processing 60.4.4.3.1. Processing a Complete Message with Tag Generation 60.4.4.3.2. Processing a Complete Message without Tag Generation 60.4.4.3.3. Processing a Fragmented Message without Tag Generation 60.4.4.3.4. Manual GCM Tag Generation 60.4.4.3.5. Processing a Message with only AAD (GHASHH) 60.4.4.3.6. Processing a Single GF128 Multiplication 60.4.5. XEX-based Tweaked-codebook Mode (XTS) 60.4.5.1. XTS Processing Procedure 60.4.5.1.1. Encrypted Tweak Generation 60.4.5.1.2. Data Processing 60.4.6. Double Input Buffer 60.4.7. Temporary Secured Storage for Keys 60.4.8. Start Modes 60.4.8.1. Manual Mode 60.4.8.2. Auto Mode 60.4.8.3. DMA Mode 60.4.9. Automatic Padding Mode 60.4.9.1. IPSEC Padding 60.4.9.2. SSL Padding 60.4.9.3. Flags 60.4.10. Secure Protocol Layers Improved Performances 60.4.10.1. Cipher Mode 60.4.10.2. Decipher Mode 60.4.10.3. Encapsulating Security Payload (ESP) IPSec Examples 60.4.11. Security Features 60.4.11.1. Unspecified Register Access Detection 60.5. Register Summary 60.5.1. AES Control Register 60.5.2. AES Mode Register 60.5.3. AES Interrupt Enable Register 60.5.4. AES Interrupt Disable Register 60.5.5. AES Interrupt Mask Register 60.5.6. AES Interrupt Status Register 60.5.7. AES Key Word Register x 60.5.8. AES Input Data Register x 60.5.9. AES Output Data Register x 60.5.10. AES Initialization Vector Register x 60.5.11. AES Additional Authenticated Data Length Register 60.5.12. AES Plaintext/Ciphertext Length Register 60.5.13. AES GCM Intermediate Hash Word Register x 60.5.14. AES GCM Authentication Tag Word Register x 60.5.15. AES GCM Encryption Counter Value Register 60.5.16. AES GCM H Word Register x 60.5.17. AES Extended Mode Register 60.5.18. AES Byte Counter Register 60.5.19. AES Tweak Word Register x 60.5.20. AES Alpha Word Register x 61. Secure Hash Algorithm (SHA) 61.1. Description 61.2. Embedded Characteristics 61.3. Product Dependencies 61.3.1. Power Management 61.3.2. Interrupt Sources 61.4. Functional Description 61.4.1. SHA Algorithm 61.4.2. HMAC Algorithm 61.4.3. Processing Period 61.4.4. Double Input Buffer 61.4.5. Internal Registers for Initial Hash Value or Expected Hash Result 61.4.6. Automatic Padding 61.4.7. Automatic Check 61.4.8. Protocol Layers Improved Performances 61.4.9. Start Modes 61.4.9.1. Manual Mode 61.4.9.2. Auto Mode 61.4.9.3. DMA Mode 61.4.9.4. SHA Register Endianness 61.4.10. Security Features 61.4.10.1. Unspecified Register Access Detection 61.5. Register Summary 61.5.1. SHA Control Register 61.5.2. SHA Mode Register 61.5.3. SHA Interrupt Enable Register 61.5.4. SHA Interrupt Disable Register 61.5.5. SHA Interrupt Mask Register 61.5.6. SHA Interrupt Status Register 61.5.7. SHA Message Size Register 61.5.8. SHA Bytes Count Register 61.5.9. SHA Input Data Register x 61.5.10. SHA Input/Output Data Register x 62. Triple Data Encryption Standard (TDES) 62.1. Description 62.2. Embedded Characteristics 62.3. Product Dependencies 62.3.1. Power Management 62.3.2. Interrupt Sources 62.4. Functional Description 62.4.1. Operating Modes 62.4.2. Temporary Secured Storage for Keys 62.4.3. Start Modes 62.4.3.1. Manual Mode 62.4.3.2. Auto Mode 62.4.3.3. DMA Mode 62.4.4. Last Output Data Mode (CBC-MAC) 62.4.4.1. Manual and Auto Modes 62.4.4.1.1. TDES_MR.LOD = 0 62.4.4.1.2. TDES_MR.LOD = 1 62.4.4.2. DMA Mode 62.4.4.2.1. TDES_MR.LOD = 0 62.4.4.2.2. TDES_MR.LOD = 1 62.4.5. Security Features 62.4.5.1. Unspecified Register Access Detection 62.5. Register Summary 62.5.1. TDES Control Register 62.5.2. TDES Mode Register 62.5.3. TDES Interrupt Enable Register 62.5.4. TDES Interrupt Disable Register 62.5.5. TDES Interrupt Mask Register 62.5.6. TDES Interrupt Status Register 62.5.7. TDES Key 1 Word Register y 62.5.8. TDES Key 2 Word Register y 62.5.9. TDES Key 3 Word Register y 62.5.10. TDES Input Data Register x 62.5.11. TDES Output Data Register x 62.5.12. TDES Initialization Vector Register x 62.5.13. TDES XTEA Rounds Register 63. True Random Number Generator (TRNG) 63.1. Description 63.2. Embedded Characteristics 63.3. Block Diagram 63.4. Product Dependencies 63.4.1. Power Management 63.4.2. Interrupt Sources 63.5. Functional Description 63.6. Register Summary 63.6.1. TRNG Control Register 63.6.2. TRNG Interrupt Enable Register 63.6.3. TRNG Interrupt Disable Register 63.6.4. TRNG Interrupt Mask Register 63.6.5. TRNG Interrupt Status Register 63.6.6. TRNG Output Data Register 64. Analog Comparator Controller (ACC) 64.1. Description 64.2. Embedded Characteristics 64.3. Block Diagram 64.4. Signal Description 64.5. Product Dependencies 64.5.1. I/O Lines 64.5.2. Power Management 64.6. Functional Description 64.6.1. Description 64.6.2. Register Write Protection 64.7. Register Summary 64.7.1. ACC Control Register 64.7.2. ACC Mode Register 64.7.3. ACC Write Protection Mode Register 64.7.4. ACC Write Protection Status Register 65. Security Module (SECUMOD) 65.1. Description 65.2. Embedded Characteristics 65.3. Block Diagram 65.3.1. I/O Lines Description 65.4. Product Dependencies 65.4.1. Interrupt Sources 65.5. Functional Description 65.5.1. Memory Mapping 65.5.2. Scrambling Keys 65.5.3. Internal Random Number Generator (IRNG) 65.5.4. Protection Mechanisms 65.5.4.1. PIO Backup Controller 65.5.4.1.1. Output Mode 65.5.4.1.2. Input Mode 65.5.4.1.3. Static Intrusion Detectors and Programmable Internal Pullup/Pulldown 65.5.4.1.4. Static Intrusion Detection 65.5.4.1.5. Internal Pullup/Pulldown 65.5.4.1.6. Scheduled Pullup/Pulldown 65.5.4.1.7. Debouncing Time 65.5.4.1.8. PIOBUx Alarm Filtering in Static Mode 65.5.4.2. JTAG Prevention 65.5.4.2.1. Debug Interface Access Prevention 65.5.4.2.2. Physical Restrictions for JTAG Debug Mode 65.5.4.2.3. Software Restrictions for JTAG Debug Mode 65.5.4.2.4. Software Prevention for JTAG Debug 65.5.5. Erasing Secure Memories 65.5.5.1. BUSRAM4KB Erase Sequence 65.5.5.1.1. Principle 65.5.5.2. BUREG256b Erase Sequence 65.5.5.2.1. During and After BUSRAM4KB and BUREG256b Erase Sequence 65.5.6. Operating Modes 65.5.6.1. Protection Unit 65.5.7. Activation or Deactivation of Protections 65.5.8. Powerup Reset 65.6. Register Summary 65.6.1. SECUMOD Control Register 65.6.2. SECUMOD System Status Register 65.6.3. SECUMOD Status Register 65.6.4. SECUMOD Status Clear Register 65.6.5. SECUMOD RAM Access Ready Register 65.6.6. SECUMOD PIO Backup Register x 65.6.7. SECUMOD JTAG Protection Control Register 65.6.8. SECUMOD Scrambling Key Register 65.6.9. SECUMOD RAM Access Rights Register 65.6.10. SECUMOD RAM Access Rights Status Register 65.6.11. SECUMOD Backup Mode Protection Register 65.6.12. SECUMOD Normal Mode Protection Register 65.6.13. SECUMOD Normal Interrupt Enable Protection Register 65.6.14. SECUMOD Normal Interrupt Disable Protection Register 65.6.15. SECUMOD Normal Interrupt Mask Protection Register 65.6.16. SECUMOD Wakeup Register 66. Analog-to-Digital Controller (ADC) 66.1. Description 66.2. Embedded Characteristics 66.3. Block Diagram 66.4. Signal Description 66.5. Product Dependencies 66.5.1. Power Management 66.5.2. Interrupt Sources 66.5.3. I/O Lines 66.5.4. Hardware Triggers 66.5.5. Fault Output 66.6. Functional Description 66.6.1. Analog-to-Digital Conversion 66.6.2. ADC Clock 66.6.3. ADC Reference Voltage 66.6.4. Conversion Resolution 66.6.5. Conversion Results 66.6.6. Conversion Results Format 66.6.7. Conversion Triggers 66.6.8. Sleep Mode and Conversion Sequencer 66.6.9. Comparison Window 66.6.10. Differential and Single-ended Input Modes 66.6.10.1. Input-output Transfer Functions 66.6.11. ADC Timings 66.6.12. Last Channel Specific Measurement Trigger 66.6.13. Enhanced Resolution Mode and Digital Averaging Function 66.6.13.1. Enhanced Resolution Mode 66.6.13.2. Averaging Function versus Trigger Events 66.6.14. Automatic Error Correction 66.6.15. Touchscreen 66.6.15.1. Touchscreen Mode 66.6.15.2. 4-wire Resistive Touchscreen Principles 66.6.15.3. 4-wire Position Measurement Method 66.6.15.4. 4-wire Pressure Measurement Method 66.6.15.5. 5-wire Resistive Touchscreen Principles 66.6.15.6. 5-wire Position Measurement Method 66.6.15.7. Sequence and Noise Filtering 66.6.15.8. Measured Values, Registers and Flags 66.6.15.9. Pen Detect Method 66.6.16. Asynchronous and Partial Wakeup (SleepWalking) 66.6.17. Buffer Structure 66.6.17.1. Classic ADC Channels Only (Touchscreen Disabled) 66.6.17.2. Touchscreen Channels Only 66.6.17.3. Interleaved Channels 66.6.17.4. Pen Detection Status 66.6.18. Fault Event 66.6.19. Register Write Protection 66.7. Register Summary 66.7.1. ADC Control Register 66.7.2. ADC Mode Register 66.7.3. ADC Channel Sequence 1 Register 66.7.4. ADC Channel Sequence 2 Register 66.7.5. ADC Channel Enable Register 66.7.6. ADC Channel Disable Register 66.7.7. ADC Channel Status Register 66.7.8. ADC Last Converted Data Register 66.7.9. ADC Interrupt Enable Register 66.7.10. ADC Interrupt Disable Register 66.7.11. ADC Interrupt Mask Register 66.7.12. ADC Interrupt Status Register 66.7.13. ADC Last Channel Trigger Mode Register 66.7.14. ADC Last Channel Compare Window Register 66.7.15. ADC Overrun Status Register 66.7.16. ADC Extended Mode Register 66.7.17. ADC Compare Window Register 66.7.18. Channel Offset Register 66.7.19. ADC Channel Data Register 66.7.20. ADC Analog Control Register 66.7.21. ADC Touchscreen Mode Register 66.7.22. ADC Touchscreen X Position Register 66.7.23. ADC Touchscreen Y Position Register 66.7.24. ADC Touchscreen Pressure Register 66.7.25. ADC Trigger Register 66.7.26. ADC Correction Values Register 66.7.27. ADC Channel Error Correction Register 66.7.28. ADC Touchscreen Correction Values Register 66.7.29. ADC Write Protection Mode Register 66.7.30. ADC Write Protection Status Register 67. Electrical Characteristics 67.1. Absolute Maximum Ratings 67.2. DC Characteristics 67.3. Power Consumption 67.4. Active Mode 67.4.1. Active Mode Power Consumption Versus Modes 67.5. Low-power Modes 67.5.1. Backup Mode 67.5.2. Backup Mode with DDR in Self-Refresh 67.5.3. Ultra Low-power (ULP) Mode 67.5.3.1. ULP0 Mode 67.5.3.2. ULP1 Mode 67.5.4. Idle Mode 67.5.5. Low-power Mode Summary Table 67.5.6. Low-power Consumption Versus Modes 67.6. Clock Characteristics 67.6.1. Processor Clock Characteristics 67.6.2. Master Clock Characteristics 67.7. Oscillator Characteristics 67.7.1. Main Oscillator Characteristics 67.7.1.1. Recommended Crystal Characteristics 67.7.1.2. XIN Clock Characteristics 67.7.2. 12 MHz RC Oscillator Characteristics 67.7.3. 32.768 kHz Crystal Oscillator Characteristics 67.7.4. 64 kHz RC Oscillator Characteristics 67.8. PLL Characteristics 67.9. USB HS Characteristics 67.9.1. Electrical Characteristics 67.9.2. Dynamic Power Consumption 67.10. PTC Characteristics 67.11. ADC Characteristics 67.11.1. ADC Power Supply 67.11.1.1. Power Supply Characteristics 67.11.1.2. ADC Bias Current 67.11.2. External Reference Voltage 67.11.3. ADC Timings 67.11.4. ADC Transfer Function 67.11.4.1. Differential Mode (12-bit mode) 67.11.4.2. Single-ended Mode (12-bit mode) 67.11.4.3. Example of LSB Computation 67.11.4.4. Gain and Offset Errors 67.11.5. ADC Electrical Characteristics 67.11.6. Pen Detect Characteristics 67.11.7. ADC Channel Input Impedance 67.12. Analog Comparator Characteristics 67.13. POR Characteristics 67.14. SMC Timings 67.14.1. Timing Conditions 67.14.2. SMC IOSET1 Timing Extraction 67.14.2.1. SMC IOSET1 Read Timings 67.14.2.2. SMC IOSET1 Write Timings 67.14.3. SMC IOSET2 Timing Extraction 67.14.3.1. SMC IOSET2 Read Timings 67.14.3.2. SMC IOSET2 Write Timings 67.15. FLEXCOM Timings 67.15.1. FLEXCOM USART in Asynchronous Modes 67.15.2. FLEXCOM SPI Timings 67.15.2.1. Timing Conditions 67.15.2.2. Timing Extraction 67.15.3. FLEXCOM TWI Timings 67.16. USART in Asynchronous Modes 67.17. SPI Timings 67.17.1. Maximum SPI Frequency 67.17.2. Timing Conditions 67.17.3. Timing Extraction 67.18. TWI Timings 67.19. QSPI Timings 67.19.1. Maximum QSPI Frequency 67.19.2. Timing Conditions 67.19.3. Timing Extraction 67.20. MPDDRC Timings 67.20.1. Board Design Constraints 67.20.2. DDR2-SDRAM 67.20.3. LPDDR1-SDRAM 67.20.4. LPDDR2/LPDDR3-SDRAM 67.20.5. DDR3/DDR3L-SDRAM 67.21. SSC Timings 67.21.1. Timing Conditions 67.21.2. Timing Extraction 67.22. PDMIC Timings 67.22.1. Timing Conditions 67.22.2. Timing Extraction 67.23. I2SC Timings 67.23.1. Timing Conditions 67.23.2. Timing Extraction 67.24. ISC Timings 67.24.1. Timing Conditions 67.24.2. Timing Extraction 67.25. SDMMC Timings 67.26. GMAC Timings 67.26.1. Timing Conditions 67.26.2. Timing Constraints 67.26.2.1. Ethernet MAC MII Mode 67.26.2.2. Ethernet MAC RMII Mode 68. Mechanical Characteristics 68.1. 289-Ball Low Profile Fine Pitch Ball Grid Array (AMB) - 14x14x1.4 mm Body [LFBGA] Atmel Legacy Global Package Code CCZ 68.2. 256-Ball Thin Fine Pitch Ball Grid Array (AYB) - 8x8x1.05 mm Body [TFBGA] 68.3. 196-Ball Thin Fine Pitch Ball Grid Array (BAB) - 11x11 mm Body [TFBGA] 69. Schematic Checklist 69.1. Power Supply 69.2. Power-On Reset 69.3. Clock, Oscillator and PLL 69.4. ICE and JTAG 69.5. Reset and Test 69.6. Shutdown/Wake-up Logic 69.7. Parallel Input/Output (PIO) 69.8. Analog-to-Digital Converter (ADC) 69.9. External Bus Interface (EBI) 69.10. USB High-Speed Host Port (UHPHS) / USB High-Speed Device Port (UDPHS) 69.11. Boot Program Hardware Constraints 69.12. Layout and Design Constraints 69.12.1. General Considerations 69.12.2. Considerations for High-Speed Differential Interfaces 69.12.3. DDR Layout and Design Considerations 69.12.4. e.MMC Routing 69.12.5. USB Trace Routing Guidelines 69.12.6. QSPI Pull-up Resistors 69.12.7. Considerations for PTC Interface 70. Marking 71. Ordering Information 72. Revision History 72.1. Revision DS60001476F - 09/2020 72.2. Revision DS60001476E - 09/2020 72.3. Revision DS60001476D - 02/2020 72.4. Revision DS60001476C 72.5. Revision DS60001476B 72.6. Revision DS60001476A 72.7. Revision 11267E 72.8. Revision 11267D 72.9. Revision 11267C 72.10. Revision 11267B 72.11. Revision 11267A The Microchip Website Product Change Notification Service Customer Support Product Identification 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