Datasheet SAM9263 (Microchip) - 10

Table 2-1. Signal Description List (Continued) Active Signal Name Function Type Level Comments LCD Controller - LCDC
LCDD0–LCDD23 LCD Data Bus Output LCDVSYNC LCD Vertical Synchronization Output LCDHSYNC LCD Horizontal Synchronization Output LCDDOTCK LCD Dot Clock Output LCDDEN LCD Data Enable Output LCDCC LCD Contrast Control Output
Ethernet 10/100 - EMAC
ETXCK Transmit Clock or Reference Clock Input MII only, REFCK in RMII ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0–ETX3 Transmit Data Output ETX0–ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input RXDV in MII, CRSDV in RMII ERX0–ERX3 Receive Data Input ERX0–ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense and Data Valid Input MII only ECOL Collision Detect Input MII only EMDC Management Data Clock Output EMDIO Management Data Input/Output I/O EF100 Force 100Mbit/sec. Output High RMII only
USB Device Port - UDP
DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog
USB Host Port - UHP
HDPA USB Host Port A Data + Analog HDMA USB Host Port A Data - Analog HDPB USB Host Port B Data + Analog HDMB USB Host Port B Data - Analog
Image Sensor Interface - ISI
ISI_D0–ISI_D11 Image Sensor Data Input ISI_MCK Image Sensor Reference Clock Output Provided by PCK3 ISI_HSYNC Image Sensor Horizontal Synchro Input ISI_VSYNC Image Sensor Vertical Synchro Input ISI_PCK Image Sensor Data Clock Input 10 SAM9263 [DATASHEET] Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16 Document Outline Description Features 1. SAM9263 Block Diagram 2. Signal Description 3. Package and Pinout 3.1 324-ball TFBGA Package Outline 3.2 324-ball TFBGA Package Pinout 4. Power Considerations 4.1 Power Supplies 4.2 Power Sequence Requirements 4.2.1 Power-up Sequence 4.2.2 Power-down Sequence 4.3 Programmable I/O Lines Power Supplies 5. I/O Line Considerations 5.1 JTAG Port Pins 5.2 Test Pin 5.3 Reset Pins 5.4 PIO Controllers 5.5 Shutdown Logic Pins 6. Processor and Architecture 6.1 ARM926EJ-S Processor 6.2 Bus Matrix 6.2.1 Matrix Masters 6.2.2 Matrix Slaves 6.2.3 Master to Slave Access 6.3 Peripheral DMA Controller 6.4 DMA Controller 6.5 Debug and Test Features 7. Memories 7.1 Embedded Memories 7.1.1 Internal Memory Mapping 7.1.1.1 Internal 80 Kbyte Fast SRAM 7.1.1.2 Internal 16 Kbyte Fast SRAM 7.1.2 Boot Strategies 7.1.2.1 BMS = 1, Boot on Embedded ROM 7.1.2.2 BMS = 0, Boot on External Memory 7.2 External Memories 7.2.1 External Bus Interfaces 7.2.1.1 External Bus Interface 0 7.2.1.2 External Bus Interface 1 7.2.2 Static Memory Controller 7.2.3 SDRAM Controller 7.2.4 Error Correction Code Controller 8. System Controller 8.1 System Controller Block Diagram 8.2 Reset Controller 8.3 Shutdown Controller 8.4 Clock Generator 8.5 Power Management Controller 8.6 Periodic Interval Timer 8.7 Watchdog Timer 8.8 Real-time Timer 8.9 General-purpose Backup Registers 8.10 Backup Power Switch 8.11 Advanced Interrupt Controller 8.12 Debug Unit 8.13 Chip Identification 8.14 PIO Controllers 9. Peripherals 9.1 User Interface 9.2 Peripheral Identifiers 9.2.1 Peripheral Interrupts and Clock Control 9.2.1.1 System Interrupt 9.2.1.2 External Interrupts 9.2.1.3 Timer Counter Interrupts 9.3 Peripherals Signals Multiplexing on I/O Lines 9.3.1 PIO Controller A Multiplexing 9.3.2 PIO Controller B Multiplexing 9.3.3 PIO Controller C Multiplexing 9.3.4 PIO Controller D Multiplexing 9.3.5 PIO Controller E Multiplexing 9.4 System Resource Multiplexing 9.4.1 LCD Controller 9.4.2 ETM™ 9.4.3 EBI1 9.4.4 Ethernet 10/100MAC 9.4.5 SSC 9.4.6 USART 9.4.7 NAND Flash 9.4.8 CompactFlash 9.4.9 SPI0 and MCI Interface 9.4.10 Interrupts 9.4.11 Image Sensor Interface 9.4.12 Timers 9.5 Embedded Peripherals Overview 9.5.1 Serial Peripheral Interface 9.5.2 Two-wire Interface 9.5.3 USART 9.5.4 Serial Synchronous Controller 9.5.5 AC97 Controller 9.5.6 Timer Counter 9.5.7 Pulse Width Modulation Controller 9.5.8 Multimedia Card Interface 9.5.9 CAN Controller 9.5.10 USB Host Port 9.5.11 USB Device Port 9.5.12 LCD Controller 9.5.13 Two D Graphics Controller 9.5.14 Ethernet 10/100 MAC 9.5.15 Image Sensor Interface 10. ARM926EJ-S Processor Overview 10.1 Overview 10.2 Block Diagram 10.3 ARM9EJ-S Processor 10.3.1 ARM9EJ-S Operating States 10.3.2 Switching State 10.3.3 Instruction Pipelines 10.3.4 Memory Access 10.3.5 Jazelle Technology 10.3.6 ARM9EJ-S Operating Modes 10.3.7 ARM9EJ-S Registers 10.3.7.1 Status Registers 10.3.7.2 Exceptions Exception Types and Priorities Exception Modes and Handling 10.3.8 ARM Instruction Set Overview 10.3.9 New ARM Instruction Set 10.3.10 Thumb Instruction Set Overview 10.4 CP15 Coprocessor 10.4.1 CP15 Registers Access 10.5 Memory Management Unit (MMU) 10.5.1 Access Control Logic 10.5.2 Translation Look-aside Buffer (TLB) 10.5.3 Translation Table Walk Hardware 10.5.4 MMU Faults 10.6 Caches and Write Buffer 10.6.1 Instruction Cache (ICache) 10.6.2 Data Cache (DCache) and Write Buffer 10.6.2.1 DCache 10.6.2.2 Write Buffer Write-though Operation Write-back Operation 10.7 Tightly-Coupled Memory Interface 10.7.1 TCM Description 10.7.2 Enabling and Disabling TCMs 10.7.3 TCM Mapping 10.8 Bus Interface Unit 10.8.1 Supported Transfers 10.8.2 Thumb Instruction Fetches 10.8.3 Address Alignment 11. SAM9263 Debug and Test 11.1 Overview 11.2 Block Diagram 11.3 Application Examples 11.3.1 Debug Environment 11.3.2 Test Environment 11.4 Debug and Test Pin Description 11.5 Functional Description 11.5.1 Test Pin 11.5.2 Embedded In-circuit Emulator 11.5.3 JTAG Signal Description 11.5.4 Debug Unit 11.5.5 Embedded Trace Macrocell (ETM) 11.5.5.1 Trace Port 11.5.5.2 Implementation Details Three-state Sequencer Address Comparator Data Comparator Memory Decoder Inputs FIFO Half-rate Clocking Mode 11.5.5.3 Application Board Restriction 11.5.6 IEEE 1149.1 JTAG Boundary Scan 11.5.6.1 JTAG Boundary Scan Register 11.5.7 ID Code Register 12. SAM9263 Boot Program 12.1 Overview 12.2 Flow Diagram 12.3 Device Initialization 12.4 DataFlash Boot 12.4.1 Valid Image Detection 12.4.2 Structure of ARM Vector 6 12.4.2.1 Example 12.4.3 DataFlash Boot Sequence 12.5 SD Card Boot 12.6 NAND Flash Boot 12.6.1 Supported NAND Flash Devices 12.7 SAM-BA Boot 12.7.1 DBGU Serial Port 12.7.2 Xmodem Protocol 12.7.3 USB Device Port 12.7.3.1 Enumeration Process 12.7.3.2 Communication Endpoints 12.8 Hardware and Software Constraints 13. Reset Controller (RSTC) 13.1 Overview 13.2 Block Diagram 13.3 Functional Description 13.3.1 Reset Controller Overview 13.3.2 NRST Manager 13.3.2.1 NRST Signal or Interrupt 13.3.2.2 NRST External Reset Control 13.3.3 BMS Sampling 13.3.4 Reset States 13.3.4.1 General Reset 13.3.4.2 Wake-up Reset 13.3.4.3 User Reset 13.3.4.4 Software Reset 13.3.4.5 Watchdog Reset 13.3.5 Reset State Priorities 13.3.6 Reset Controller Status Register 13.4 Reset Controller (RSTC) User Interface 13.4.1 Reset Controller Control Register 13.4.2 Reset Controller Status Register 13.4.3 Reset Controller Mode Register 14. Real-time Timer (RTT) 14.1 Description 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Functional Description 14.5 Real-time Timer (RTT) User Interface 14.5.1 Real-time Timer Mode Register 14.5.2 Real-time Timer Alarm Register 14.5.3 Real-time Timer Value Register 14.5.4 Real-time Timer Status Register 15. Periodic Interval Timer (PIT) 15.1 Description 15.2 Embedded Characteristics 15.3 Block Diagram 15.4 Functional Description 15.5 Periodic Interval Timer (PIT) User Interface 15.5.1 Periodic Interval Timer Mode Register 15.5.2 Periodic Interval Timer Status Register 15.5.3 Periodic Interval Timer Value Register 15.5.4 Periodic Interval Timer Image Register 16. Watchdog Timer (WDT) 16.1 Description 16.2 Embedded Characteristics 16.3 Block Diagram 16.4 Functional Description 16.5 Watchdog Timer (WDT) User Interface 16.5.1 Watchdog Timer Control Register 16.5.2 Watchdog Timer Mode Register 16.5.3 Watchdog Timer Status Register 17. Shutdown Controller (SHDWC) 17.1 Description 17.2 Embedded Characteristics 17.3 Block Diagram 17.4 I/O Lines Description 17.5 Product Dependencies 17.5.1 Power Management 17.6 Functional Description 17.7 Shutdown Controller (SHDWC) User Interface 17.7.1 Shutdown Control Register 17.7.2 Shutdown Mode Register 17.7.3 Shutdown Status Register 18. General Purpose Backup Registers (GPBR) 18.1 Overview 18.2 General Purpose Backup Registers (GPBR) User Interface 18.2.1 General Purpose Backup Register x 19. SAM9263 Bus Matrix 19.1 Description 19.2 Memory Mapping 19.3 Special Bus Granting Techniques 19.3.1 No Default Master 19.3.2 Last Access Master 19.3.3 Fixed Default Master 19.4 Arbitration 19.4.1 Arbitration rules 19.4.1.1 Undefined Length Burst Arbitration 19.4.1.2 Slot Cycle Limit Arbitration 19.4.2 Round-Robin Arbitration 19.4.2.1 Round-Robin Arbitration without Default Master 19.4.2.2 Round-Robin Arbitration with Last Access Master 19.4.2.3 Round-Robin Arbitration with Fixed Default Master 19.4.3 Fixed Priority Arbitration 19.5 Bus Matrix User Interface 19.5.1 Bus Matrix Master Configuration Registers 19.5.2 Bus Matrix Slave Configuration Registers 19.5.3 Bus Matrix Priority Registers A For Slaves 19.5.4 Bus Matrix Priority Registers B For Slaves 19.5.5 Bus Matrix Master Remap Control Register 19.6 Chip Configuration User Interface 19.6.1 Bus Matrix TCM Configuration Register 19.6.2 EBI0 Chip Select Assignment Register 19.6.3 EBI1 Chip Select Assignment Register 20. External Bus Interface (EBI) 20.1 Overview 20.2 Block Diagram 20.2.1 External Bus Interface 0 20.2.2 External Bus Interface 1 20.3 I/O Lines Description 20.3.1 Hardware Interface 20.3.2 Connection Examples 20.4 Product Dependencies 20.4.1 I/O Lines 20.5 Functional Description 20.5.1 Bus Multiplexing 20.5.2 Pull-up Control 20.5.3 Static Memory Controller 20.5.4 SDRAM Controller 20.5.5 ECC Controller 20.5.6 CompactFlash Support (EBI0 only) 20.5.6.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode 20.5.6.2 CFCE1 and CFCE2 Signals 20.5.6.3 Read/Write Signals 20.5.6.4 Multiplexing of CompactFlash Signals on EBI Pins 20.5.6.5 Application Example 20.5.7 NAND Flash Support 20.5.7.1 External Bus Interface 0 20.5.7.2 External Bus Interface 1 20.5.7.3 NAND Flash Signals 20.6 Implementation Examples 20.6.1 16-bit SDRAM 20.6.1.1 Hardware Configuration - 16-bit SDRAM 20.6.1.2 Software Configuration - 16-bit SDRAM 20.6.2 32-bit SDRAM 20.6.2.1 Hardware Configuration - 32-bit SDRAM 20.6.2.2 Software Configuration - 32-bit SDRAM 20.6.3 8-bit NAND Flash 20.6.3.1 Hardware Configuration - 8-bit NAND Flash 20.6.3.2 Software Configuration - 8-bit NAND Flash 20.6.4 16-bit NAND Flash 20.6.4.1 Hardware Configuration - 16-bit NAND Flash 20.6.4.2 Software Configuration - 16-bit NAND Flash 20.6.5 NOR Flash on NCS0 20.6.5.1 Hardware Configuration - NOR Flash on NCS0 20.6.5.2 Software Configuration - NOR Flash on NCS0 20.6.6 CompactFlash 20.6.6.1 Hardware Configuration - CompactFlash 20.6.6.2 Software Configuration - CompactFlash 20.6.7 CompactFlash True IDE 20.6.7.1 Hardware Configuration - CompactFlash True IDE 20.6.7.2 Software Configuration - CompactFlash True IDE 21. Static Memory Controller (SMC) 21.1 Overview 21.2 I/O Lines Description 21.3 Multiplexed Signals 21.4 Application Example 21.4.1 Hardware Interface 21.5 Product Dependencies 21.5.1 I/O Lines 21.6 External Memory Mapping 21.7 Connection to External Devices 21.7.1 Data Bus Width 21.7.2 Byte Write or Byte Select Access 21.7.2.1 Byte Write Access 21.7.2.2 Byte Select Access 21.7.2.3 Signal Multiplexing 21.8 Standard Read and Write Protocols 21.8.1 Read Waveforms 21.8.1.1 NRD Waveform 21.8.1.2 NCS Waveform 21.8.1.3 Read Cycle 21.8.1.4 Null Delay Setup and Hold 21.8.1.5 Null Pulse 21.8.2 Read Mode 21.8.2.1 Read is Controlled by NRD (READ_MODE = 1): 21.8.2.2 Read is Controlled by NCS (READ_MODE = 0) 21.8.3 Write Waveforms 21.8.3.1 NWE Waveforms 21.8.3.2 NCS Waveforms 21.8.3.3 Write Cycle 21.8.3.4 Null Delay Setup and Hold 21.8.3.5 Null Pulse 21.8.4 Write Mode 21.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1) 21.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 21.8.5 Coding Timing Parameters 21.8.6 Reset Values of Timing Parameters 21.8.7 Usage Restriction 21.9 Automatic Wait States 21.9.1 Chip Select Wait States 21.9.2 Early Read Wait State 21.9.3 Reload User Configuration Wait State 21.9.3.1 User Procedure 21.9.3.2 Slow Clock Mode Transition 21.9.4 Read to Write Wait State 21.10 Data Float Wait States 21.10.1 READ_MODE 21.10.2 TDF Optimization Enabled (TDF_MODE = 1) 21.10.3 TDF Optimization Disabled (TDF_MODE = 0) 21.11 External Wait 21.11.1 Restriction 21.11.2 Frozen Mode 21.11.3 Ready Mode 21.11.4 NWAIT Latency and Read/Write Timings 21.12 Slow Clock Mode 21.12.1 Slow Clock Mode Waveforms 21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 21.13 Asynchronous Page Mode 21.13.1 Protocol and Timings in Page Mode 21.13.2 Byte Access Type in Page Mode 21.13.3 Page Mode Restriction 21.13.4 Sequential and Non-sequential Accesses 21.14 Static Memory Controller (SMC) User Interface 21.14.1 SMC Setup Register 21.14.2 SMC Pulse Register 21.14.3 SMC Cycle Register 21.14.4 SMC Mode Register 22. SDRAM Controller (SDRAMC) 22.1 Description 22.2 I/O Lines Description 22.3 Application Example 22.3.1 Software Interface 22.3.1.1 32-bit Memory Data Bus Width 22.3.1.2 16-bit Memory Data Bus Width 22.4 Product Dependencies 22.4.1 SDRAM Device Initialization 22.4.2 I/O Lines 22.4.3 Interrupt 22.5 Functional Description 22.5.1 SDRAM Controller Write Cycle 22.5.2 SDRAM Controller Read Cycle 22.5.3 Border Management 22.5.4 SDRAM Controller Refresh Cycles 22.5.5 Power Management 22.5.5.1 Self-refresh Mode 22.5.5.2 Low-power Mode 22.5.5.3 Deep Power-down Mode 22.6 SDRAM Controller (SDRAMC) User Interface 22.6.1 SDRAMC Mode Register 22.6.2 SDRAMC Refresh Timer Register 22.6.3 SDRAMC Configuration Register 22.6.4 SDRAMC Low Power Register 22.6.5 SDRAMC Interrupt Enable Register 22.6.6 SDRAMC Interrupt Disable Register 22.6.7 SDRAMC Interrupt Mask Register 22.6.8 SDRAMC Interrupt Status Register 22.6.9 SDRAMC Memory Device Register 23. Error Correction Code Controller (ECC) 23.1 Description 23.2 Block Diagram 23.3 Functional Description 23.3.1 Write Access 23.3.2 Read Access 23.4 Error Correction Code Controller (ECC) User Interface 23.4.1 ECC Control Register 23.4.2 ECC Mode Register 23.4.3 ECC Status Register 23.4.4 ECC Parity Register 23.4.5 ECC NParity Register 24. DMA Controller (DMAC) 24.1 Overview 24.2 Block Diagram 24.3 Functional Description 24.3.1 Basic Definitions 24.3.2 Memory Peripherals 24.3.3 Handshaking Interface 24.3.3.1 Software Handshaking Burst Transactions Single Transactions 24.3.3.2 Hardware Handshaking External DMA Request Definition 24.3.4 DMAC Transfer Types 24.3.4.1 Multi-block Transfers Block Chaining Using Linked Lists Auto-reloading of Channel Registers Contiguous Address Between Blocks Suspension of Transfers Between Blocks 24.3.4.2 Ending Multi-block Transfers 24.3.5 Programming a Channel 24.3.5.1 Programming Examples Single-block Transfer (Row 1) Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10) Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4) Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 7) Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8) 24.3.6 Disabling a Channel Prior to Transfer Completion 24.3.6.1 Abnormal Transfer Termination 24.4 DMA Controller (DMAC) User Interface 24.4.1 Channel x Source Address Register 24.4.2 Channel x Destination Address Register 24.4.3 Linked List Pointer Register for Channel x 24.4.4 Control Register for Channel x Low 24.4.5 Control Register for Channel x High 24.4.6 Configuration Register for Channel x Low 24.4.7 Configuration Register for Channel x High 24.4.8 Source Gather Register for Channel x 24.4.9 Destination Scatter Register for Channel x 24.4.10 Interrupt Registers 24.4.11 Interrupt Raw Status Registers 24.4.12 Interrupt Status Registers 24.4.13 Interrupt Mask Registers 24.4.14 Interrupt Clear Registers 24.4.15 Combined Interrupt Status Registers 24.4.16 Source Software Transaction Request Register 24.4.17 Destination Software Transaction Request Register 24.4.18 Single Source Transaction Request Register 24.4.19 Single Destination Transaction Request Register 24.4.20 Last Source Transaction Request Register 24.4.21 Last Destination Transaction Request Register 24.4.22 DMAC Configuration Register 24.4.23 DMAC Channel Enable Register 25. Peripheral DMA Controller (PDC) 25.1 Description 25.2 Block Diagram 25.3 Functional Description 25.3.1 Configuration 25.3.2 Memory Pointers 25.3.3 Transfer Counters 25.3.4 Data Transfers 25.3.5 PDC Flags and Peripheral Status Register 25.3.5.1 Receive Transfer End 25.3.5.2 Transmit Transfer End 25.3.5.3 Receive Buffer Full 25.3.5.4 Transmit Buffer Empty 25.4 Peripheral DMA Controller (PDC) User Interface 25.4.1 Receive Pointer Register 25.4.2 Receive Counter Register 25.4.3 Transmit Pointer Register 25.4.4 Transmit Counter Register 25.4.5 Receive Next Pointer Register 25.4.6 Receive Next Counter Register 25.4.7 Transmit Next Pointer Register 25.4.8 Transmit Next Counter Register 25.4.9 Transfer Control Register 25.4.10 Transfer Status Register 26. Clock Generator 26.1 Overview 26.2 Slow Clock Crystal Oscillator 26.3 Main Oscillator 26.3.1 Main Oscillator Connections 26.3.2 Main Oscillator Startup Time 26.3.3 Main Oscillator Control 26.3.4 Main Clock Frequency Counter 26.3.5 Main Oscillator Bypass 26.4 Divider and PLL Block 26.4.1 PLL Filter 26.4.2 Divider and Phase Lock Loop Programming 27. Power Management Controller (PMC) 27.1 Overview 27.2 Master Clock Controller 27.3 Processor Clock Controller 27.4 USB Clock Controller 27.5 Peripheral Clock Controller 27.6 Programmable Clock Output Controller 27.7 Programming Sequence 27.8 Clock Switching Details 27.8.1 Master Clock Switching Timings 27.8.2 Clock Switching Waveforms 27.9 Power Management Controller (PMC) User Interface 27.9.1 PMC System Clock Enable Register 27.9.2 PMC System Clock Disable Register 27.9.3 PMC System Clock Status Register 27.9.4 PMC Peripheral Clock Enable Register 27.9.5 PMC Peripheral Clock Disable Register 27.9.6 PMC Peripheral Clock Status Register 27.9.7 PMC Clock Generator Main Oscillator Register 27.9.8 PMC Clock Generator Main Clock Frequency Register 27.9.9 PMC Clock Generator PLL A Register 27.9.10 PMC Clock Generator PLL B Register 27.9.11 PMC Master Clock Register 27.9.12 PMC Programmable Clock Register 27.9.13 PMC Interrupt Enable Register 27.9.14 PMC Interrupt Disable Register 27.9.15 PMC Status Register 27.9.16 PMC Interrupt Mask Register 27.9.17 PLL Charge Pump Current Register 28. Advanced Interrupt Controller (AIC) 28.1 Overview 28.2 Block Diagram 28.3 Application Block Diagram 28.4 AIC Detailed Block Diagram 28.5 I/O Line Description 28.6 Product Dependencies 28.6.1 I/O Lines 28.6.2 Power Management 28.6.3 Interrupt Sources 28.7 Functional Description 28.7.1 Interrupt Source Control 28.7.1.1 Interrupt Source Mode 28.7.1.2 Interrupt Source Enabling 28.7.1.3 Interrupt Clearing and Setting 28.7.1.4 Interrupt Status 28.7.1.5 Internal Interrupt Source Input Stage 28.7.1.6 External Interrupt Source Input Stage 28.7.2 Interrupt Latencies 28.7.2.1 External Interrupt Edge Triggered Source 28.7.2.2 External Interrupt Level Sensitive Source 28.7.2.3 Internal Interrupt Edge Triggered Source 28.7.2.4 Internal Interrupt Level Sensitive Source 28.7.3 Normal Interrupt 28.7.3.1 Priority Controller 28.7.3.2 Interrupt Nesting 28.7.3.3 Interrupt Vectoring 28.7.3.4 Interrupt Handlers 28.7.4 Fast Interrupt 28.7.4.1 Fast Interrupt Source 28.7.4.2 Fast Interrupt Control 28.7.4.3 Fast Interrupt Vectoring 28.7.4.4 Fast Interrupt Handlers 28.7.4.5 Fast Forcing 28.7.5 Protect Mode 28.7.6 Spurious Interrupt 28.7.7 General Interrupt Mask 28.8 Advanced Interrupt Controller (AIC) User Interface 28.8.1 Base Address 28.8.2 AIC Source Mode Register 28.8.3 AIC Source Vector Register 28.8.4 AIC Interrupt Vector Register 28.8.5 AIC FIQ Vector Register 28.8.6 AIC Interrupt Status Register 28.8.7 AIC Interrupt Pending Register 28.8.8 AIC Interrupt Mask Register 28.8.9 AIC Core Interrupt Status Register 28.8.10 AIC Interrupt Enable Command Register 28.8.11 AIC Interrupt Disable Command Register 28.8.12 AIC Interrupt Clear Command Register 28.8.13 AIC Interrupt Set Command Register 28.8.14 AIC End of Interrupt Command Register 28.8.15 AIC Spurious Interrupt Vector Register 28.8.16 AIC Debug Control Register 28.8.17 AIC Fast Forcing Enable Register 28.8.18 AIC Fast Forcing Disable Register 28.8.19 AIC Fast Forcing Status Register 29. Debug Unit (DBGU) 29.1 Description 29.2 Embedded Characteristics 29.3 Block Diagram 29.4 Product Dependencies 29.4.1 I/O Lines 29.4.2 Power Management 29.4.3 Interrupt Source 29.5 UART Operations 29.5.1 Baud Rate Generator 29.5.2 Receiver 29.5.2.1 Receiver Reset, Enable and Disable 29.5.2.2 Start Detection and Data Sampling 29.5.2.3 Receiver Ready 29.5.2.4 Receiver Overrun 29.5.2.5 Parity Error 29.5.2.6 Receiver Framing Error 29.5.3 Transmitter 29.5.3.1 Transmitter Reset, Enable and Disable 29.5.3.2 Transmit Format 29.5.3.3 Transmitter Control 29.5.4 Peripheral Data Controller 29.5.5 Test Modes 29.5.6 Debug Communication Channel Support 29.5.7 Chip Identifier 29.5.8 ICE Access Prevention 29.6 Debug Unit (DBGU) User Interface 29.6.1 Debug Unit Control Register 29.6.2 Debug Unit Mode Register 29.6.3 Debug Unit Interrupt Enable Register 29.6.4 Debug Unit Interrupt Disable Register 29.6.5 Debug Unit Interrupt Mask Register 29.6.6 Debug Unit Status Register 29.6.7 Debug Unit Receiver Holding Register 29.6.8 Debug Unit Transmit Holding Register 29.6.9 Debug Unit Baud Rate Generator Register 29.6.10 Debug Unit Chip ID Register 29.6.11 Debug Unit Chip ID Extension Register 29.6.12 Debug Unit Force NTRST Register 30. Parallel Input/Output Controller (PIO) 30.1 Description 30.2 Block Diagram 30.3 Product Dependencies 30.3.1 Pin Multiplexing 30.3.2 External Interrupt Lines 30.3.3 Power Management 30.3.4 Interrupt Generation 30.4 Functional Description 30.4.1 Pull-up Resistor Control 30.4.2 I/O Line or Peripheral Function Selection 30.4.3 Peripheral A or B Selection 30.4.4 Output Control 30.4.5 Synchronous Data Output 30.4.6 Multi Drive Control (Open Drain) 30.4.7 Output Line Timings 30.4.8 Inputs 30.4.9 Input Glitch Filtering 30.4.10 Input Change Interrupt 30.5 I/O Lines Programming Example 30.6 Parallel Input/Output Controller (PIO) User Interface 30.6.1 PIO Controller PIO Enable Register 30.6.2 PIO Controller PIO Disable Register 30.6.3 PIO Controller PIO Status Register 30.6.4 PIO Controller Output Enable Register 30.6.5 PIO Controller Output Disable Register 30.6.6 PIO Controller Output Status Register 30.6.7 PIO Controller Input Filter Enable Register 30.6.8 PIO Controller Input Filter Disable Register 30.6.9 PIO Controller Input Filter Status Register 30.6.10 PIO Controller Set Output Data Register 30.6.11 PIO Controller Clear Output Data Register 30.6.12 PIO Controller Output Data Status Register 30.6.13 PIO Controller Pin Data Status Register 30.6.14 PIO Controller Interrupt Enable Register 30.6.15 PIO Controller Interrupt Disable Register 30.6.16 PIO Controller Interrupt Mask Register 30.6.17 PIO Controller Interrupt Status Register 30.6.18 PIO Multi-driver Enable Register 30.6.19 PIO Multi-driver Disable Register 30.6.20 PIO Multi-driver Status Register 30.6.21 PIO Pull Up Disable Register 30.6.22 PIO Pull Up Enable Register 30.6.23 PIO Pull Up Status Register 30.6.24 PIO Peripheral A Select Register 30.6.25 PIO Peripheral B Select Register 30.6.26 PIO Peripheral A B Status Register 30.6.27 PIO Output Write Enable Register 30.6.28 PIO Output Write Disable Register 30.6.29 PIO Output Write Status Register 31. Serial Peripheral Interface (SPI) 31.1 Overview 31.2 Block Diagram 31.3 Application Block Diagram 31.4 Signal Description 31.5 Product Dependencies 31.5.1 I/O Lines 31.5.2 Power Management 31.5.3 Interrupt 31.6 Functional Description 31.6.1 Modes of Operation 31.6.2 Data Transfer 31.6.3 Master Mode Operations 31.6.3.1 Master Mode Block Diagram 31.6.3.2 Master Mode Flow Diagram 31.6.3.3 Clock Generation 31.6.3.4 Transfer Delays 31.6.3.5 Peripheral Selection 31.6.3.6 Peripheral Chip Select Decoding 31.6.3.7 Peripheral Deselection 31.6.3.8 Mode Fault Detection 31.6.4 SPI Slave Mode 31.7 Serial Peripheral Interface (SPI) User Interface 31.7.1 SPI Control Register 31.7.2 SPI Mode Register 31.7.3 SPI Receive Data Register 31.7.4 SPI Transmit Data Register 31.7.5 SPI Status Register 31.7.6 SPI Interrupt Enable Register 31.7.7 SPI Interrupt Disable Register 31.7.8 SPI Interrupt Mask Register 31.7.9 SPI Chip Select Register 32. Two-wire Interface (TWI) 32.1 Description 32.2 Embedded Characteristics 32.3 List of Abbreviations 32.4 Block Diagram 32.5 Application Block Diagram 32.6 I/O Lines Description 32.7 Product Dependencies 32.7.1 I/O Lines 32.7.2 Power Management 32.7.3 Interrupt 32.8 Functional Description 32.8.1 Transfer format 32.8.2 Modes of Operation 32.8.3 Master Transmitter Mode 32.8.4 Master Receiver Mode 32.8.5 Internal Address 32.8.5.1 7-bit Slave Addressing 32.8.5.2 10-bit Slave Addressing 32.8.6 Read/Write Flowcharts 32.9 Two-wire Interface (TWI) User Interface 32.9.1 TWI Control Register 32.9.2 TWI Master Mode Register 32.9.3 TWI Internal Address Register 32.9.4 TWI Clock Waveform Generator Register 32.9.5 TWI Status Register 32.9.6 TWI Interrupt Enable Register 32.9.7 TWI Interrupt Disable Register 32.9.8 TWI Interrupt Mask Register 32.9.9 TWI Receive Holding Register 32.9.10 TWI Transmit Holding Register 33. Universal Synchronous Asynchronous Receiver Transmitter (USART) 33.1 Overview 33.2 Block Diagram 33.3 Application Block Diagram 33.4 I/O Lines Description 33.5 Product Dependencies 33.5.1 I/O Lines 33.5.2 Power Management 33.5.3 Interrupt 33.6 Functional Description 33.6.1 Baud Rate Generator 33.6.1.1 Baud Rate in Asynchronous Mode 33.6.1.2 Baud Rate Calculation Example 33.6.1.3 Fractional Baud Rate in Asynchronous Mode 33.6.1.4 Baud Rate in Synchronous Mode 33.6.1.5 Baud Rate in ISO 7816 Mode 33.6.2 Receiver and Transmitter Control 33.6.3 Synchronous and Asynchronous Modes 33.6.3.1 Transmitter Operations 33.6.3.2 Asynchronous Receiver 33.6.3.3 Synchronous Receiver 33.6.3.4 Receiver Operations 33.6.3.5 Parity 33.6.3.6 Multidrop Mode 33.6.3.7 Transmitter Timeguard 33.6.3.8 Receiver Time-out 33.6.3.9 Framing Error 33.6.3.10 Transmit Break 33.6.3.11 Receive Break 33.6.3.12 Hardware Handshaking 33.6.4 ISO7816 Mode 33.6.4.1 ISO7816 Mode Overview 33.6.4.2 Protocol T = 0 Receive Error Counter Receive NACK Inhibit Transmit Character Repetition Disable Successive Receive NACK 33.6.4.3 Protocol T = 1 33.6.5 IrDA Mode 33.6.5.1 IrDA Modulation 33.6.5.2 IrDA Baud Rate 33.6.5.3 IrDA Demodulator 33.6.6 RS485 Mode 33.6.7 Test Modes 33.6.7.1 Normal Mode 33.6.7.2 Automatic Echo Mode 33.6.7.3 Local Loopback Mode 33.6.7.4 Remote Loopback Mode 33.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 33.7.1 USART Control Register 33.7.2 USART Mode Register 33.7.3 USART Interrupt Enable Register 33.7.4 USART Interrupt Disable Register 33.7.5 USART Interrupt Mask Register 33.7.6 USART Channel Status Register 33.7.7 USART Receive Holding Register 33.7.8 USART Transmit Holding Register 33.7.9 USART Baud Rate Generator Register 33.7.10 USART Receiver Time-out Register 33.7.11 USART Transmitter Timeguard Register 33.7.12 USART FI DI RATIO Register 33.7.13 USART Number of Errors Register 33.7.14 USART IrDA FILTER Register 34. Synchronous Serial Controller (SSC) 34.1 Overview 34.2 Block Diagram 34.3 Application Block Diagram 34.4 Pin Name List 34.5 Product Dependencies 34.5.1 I/O Lines 34.5.2 Power Management 34.5.3 Interrupt 34.6 Functional Description 34.6.1 Clock Management 34.6.1.1 Clock Divider 34.6.1.2 Transmitter Clock Management 34.6.1.3 Receiver Clock Management 34.6.1.4 Serial Clock Ratio Considerations 34.6.2 Transmitter Operations 34.6.3 Receiver Operations 34.6.4 Start 34.6.5 Frame Sync 34.6.5.1 Frame Sync Data 34.6.5.2 Frame Sync Edge Detection 34.6.6 Receive Compare Modes 34.6.6.1 Compare Functions 34.6.7 Data Format 34.6.8 Loop Mode 34.6.9 Interrupt 34.7 SSC Application Examples 34.8 Synchronous Serial Controller (SSC) User Interface 34.8.1 SSC Control Register 34.8.2 SSC Clock Mode Register 34.8.3 SSC Receive Clock Mode Register 34.8.4 SSC Receive Frame Mode Register 34.8.5 SSC Transmit Clock Mode Register 34.8.6 SSC Transmit Frame Mode Register 34.8.7 SSC Receive Holding Register 34.8.8 SSC Transmit Holding Register 34.8.9 SSC Receive Synchronization Holding Register 34.8.10 SSC Transmit Synchronization Holding Register 34.8.11 SSC Receive Compare 0 Register 34.8.12 SSC Receive Compare 1 Register 34.8.13 SSC Status Register 34.8.14 SSC Interrupt Enable Register 34.8.15 SSC Interrupt Disable Register 34.8.16 SSC Interrupt Mask Register 35. AC97 Controller (AC97C) 35.1 Overview 35.2 Block Diagram 35.3 Pin Name List 35.4 Application Block Diagram 35.5 Product Dependencies 35.5.1 I/O Lines 35.5.2 Power Management 35.5.3 Interrupt 35.6 Functional Description 35.6.1 Protocol overview 35.6.1.1 Slot Description 35.6.1.2 Tag Slot 35.6.1.3 Codec Slot 1 35.6.1.4 Codec Slot 2 35.6.1.5 Data Slots [3:12] 35.6.2 AC97 Controller Channel Organization 35.6.2.1 AC97 Controller Setup 35.6.2.2 Transmit Operation 35.6.2.3 AC97 Output Frame 35.6.2.4 Receive Operation 35.6.2.5 AC97 Input Frame 35.6.2.6 Configuring and Using Interrupts 35.6.2.7 Endianness 35.6.2.8 To Transmit a Word Stored in Big Endian Format on AC-link 35.6.2.9 To Transmit A Halfword Stored in Big Indian Format on AC-link 35.6.2.10 To Transmit a10-bit Sample Stored in Big Endian Format on AC-link 35.6.2.11 To Receive Word transfers 35.6.2.12 To Receive Halfword Transfers 35.6.2.13 To Receive 10-bit Samples 35.6.3 Variable Sample Rate 35.6.4 Power Management 35.6.4.1 Powering Down the AC-Link 35.6.4.2 Waking up the AC-link 35.6.4.3 Wake-up Triggered by the AC97 Controller 35.6.4.4 Wake-up Triggered by the AC97 Codec 35.6.4.5 AC97 Codec Reset 35.6.4.6 Cold AC97 Reset 35.6.4.7 Warm AC97 Reset 35.7 AC97 Controller (AC97C) User Interface 35.7.1 AC97 Controller Mode Register 35.7.2 AC97 Controller Input Channel Assignment Register 35.7.3 AC97 Controller Output Channel Assignment Register 35.7.4 AC97 Controller Codec Channel Receive Holding Register 35.7.5 AC97 Controller Codec Channel Transmit Holding Register 35.7.6 AC97 Controller Channel A, Channel B, Receive Holding Register 35.7.7 AC97 Controller Channel A, Channel B, Transmit Holding Register 35.7.8 AC97 Controller Channel A Status Register 35.7.9 AC97 Controller Channel B Status Register 35.7.10 AC97 Controller Codec Status Register 35.7.11 AC97 Controller Channel A Mode Register 35.7.12 AC97 Controller Channel B Mode Register 35.7.13 AC97 Controller Codec Mode Register 35.7.14 AC97 Controller Status Register 35.7.15 AC97 Codec Controller Interrupt Enable Register 35.7.16 AC97 Controller Interrupt Disable Register 35.7.17 AC97 Controller Interrupt Mask Register 36. Controller Area Network (CAN) 36.1 Overview 36.2 Block Diagram 36.3 Application Block Diagram 36.4 I/O Lines Description 36.5 Product Dependencies 36.5.1 I/O Lines 36.5.2 Power Management 36.5.3 Interrupt 36.6 CAN Controller Features 36.6.1 CAN Protocol Overview 36.6.2 Mailbox Organization 36.6.2.1 Message Acceptance Procedure 36.6.2.2 Receive Mailbox 36.6.2.3 Transmit Mailbox 36.6.3 Time Management Unit 36.6.4 CAN 2.0 Standard Features 36.6.4.1 CAN Bit Timing Configuration 36.6.4.2 CAN Bus Synchronization 36.6.4.3 Autobaud Mode 36.6.4.4 Error Detection 36.6.4.5 Fault Confinement 36.6.4.6 Error Interrupt Handler 36.6.4.7 Overload 36.6.5 Low-power Mode 36.6.5.1 Enabling Low-power Mode 36.6.5.2 Disabling Low-power Mode 36.7 Functional Description 36.7.1 CAN Controller Initialization 36.7.2 CAN Controller Interrupt Handling 36.7.3 CAN Controller Message Handling 36.7.3.1 Receive Handling 36.7.3.2 Simple Receive Mailbox 36.7.3.3 Receive with Overwrite Mailbox 36.7.3.4 Chaining Mailboxes 36.7.3.5 Transmission Handling 36.7.3.6 Remote Frame Handling 36.7.3.7 Producer Configuration 36.7.3.8 Consumer Configuration 36.7.4 CAN Controller Timing Modes 36.7.4.1 Timestamping Mode 36.7.4.2 Time Triggered Mode 36.7.4.3 Synchronization by a Reference Message 36.7.4.4 Transmitting within a Time Window 36.7.4.5 Freezing the Internal Timer Counter 36.8 Controller Area Network (CAN) User Interface 36.8.1 CAN Mode Register 36.8.2 CAN Interrupt Enable Register 36.8.3 CAN Interrupt Disable Register 36.8.4 CAN Interrupt Mask Register 36.8.5 CAN Status Register 36.8.6 CAN Baudrate Register 36.8.7 CAN Timer Register 36.8.8 CAN Timestamp Register 36.8.9 CAN Error Counter Register 36.8.10 CAN Transfer Command Register 36.8.11 CAN Abort Command Register 36.8.12 CAN Message Mode Register 36.8.13 CAN Message Acceptance Mask Register 36.8.14 CAN Message ID Register 36.8.15 CAN Message Family ID Register 36.8.16 CAN Message Status Register 36.8.17 CAN Message Data Low Register 36.8.18 CAN Message Data High Register 36.8.19 CAN Message Control Register 37. Pulse Width Modulation Controller (PWM) 37.1 Overview 37.2 Block Diagram 37.3 I/O Lines Description 37.4 Product Dependencies 37.4.1 I/O Lines 37.4.2 Power Management 37.4.3 Interrupt Sources 37.5 Functional Description 37.5.1 PWM Clock Generator 37.5.2 PWM Channel 37.5.2.1 Block Diagram 37.5.2.2 Waveform Properties 37.5.3 PWM Controller Operations 37.5.3.1 Initialization 37.5.3.2 Source Clock Selection Criteria 37.5.3.3 Changing the Duty Cycle or the Period 37.5.3.4 Interrupts 37.6 Pulse Width Modulation Controller (PWM) User Interface 37.6.1 PWM Mode Register 37.6.2 PWM Enable Register 37.6.3 PWM Disable Register 37.6.4 PWM Status Register 37.6.5 PWM Interrupt Enable Register 37.6.6 PWM Interrupt Disable Register 37.6.7 PWM Interrupt Mask Register 37.6.8 PWM Interrupt Status Register 37.6.9 PWM Channel Mode Register 37.6.10 PWM Channel Duty Cycle Register 37.6.11 PWM Channel Period Register 37.6.12 PWM Channel Counter Register 37.6.13 PWM Channel Update Register 38. Timer Counter (TC) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 Pin Name List 38.5 Product Dependencies 38.5.1 I/O Lines 38.5.2 Power Management 38.5.3 Interrupt 38.6 Functional Description 38.6.1 TC Description 38.6.2 16-bit Counter 38.6.3 Clock Selection 38.6.4 Clock Control 38.6.5 TC Operating Modes 38.6.6 Trigger 38.6.7 Capture Operating Mode 38.6.8 Capture Registers A and B 38.6.9 Trigger Conditions 38.6.10 Waveform Operating Mode 38.6.11 Waveform Selection 38.6.11.1 WAVSEL = 00 38.6.11.2 WAVSEL = 10 38.6.11.3 WAVSEL = 01 38.6.11.4 WAVSEL = 11 38.6.12 External Event/Trigger Conditions 38.6.13 Output Controller 38.7 Timer Counter (TC) User Interface 38.7.1 TC Block Control Register 38.7.2 TC Block Mode Register 38.7.3 TC Channel Control Register 38.7.4 TC Channel Mode Register: Capture Mode 38.7.5 TC Channel Mode Register: Waveform Mode 38.7.6 TC Counter Value Register 38.7.7 TC Register A 38.7.8 TC Register B 38.7.9 TC Register C 38.7.10 TC Status Register 38.7.11 TC Interrupt Enable Register 38.7.12 TC Interrupt Disable Register 38.7.13 TC Interrupt Mask Register 39. MultiMedia Card Interface (MCI) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 Application Block Diagram 39.5 Pin Name List 39.6 Product Dependencies 39.6.1 I/O Lines 39.6.2 Power Management 39.6.3 Interrupt 39.7 Bus Topology 39.8 MultiMedia Card Operations 39.8.1 Command - Response Operation 39.8.2 Data Transfer Operation 39.8.3 Read Operation 39.8.4 Write Operation 39.9 SD/SDIO Card Operations 39.9.1 SDIO Data Transfer Type 39.9.2 SDIO Interrupts 39.10 MultiMedia Card Interface (MCI) User Interface 39.10.1 MCI Control Register 39.10.2 MCI Mode Register 39.10.3 MCI Data Timeout Register 39.10.4 MCI SDCard/SDIO Register 39.10.5 MCI Argument Register 39.10.6 MCI Command Register 39.10.7 MCI Block Register 39.10.8 MCI Response Register 39.10.9 MCI Receive Data Register 39.10.10 MCI Transmit Data Register 39.10.11 MCI Status Register 39.10.12 MCI Interrupt Enable Register 39.10.13 MCI Interrupt Disable Register 39.10.14 MCI Interrupt Mask Register 40. Ethernet MAC 10/100 (EMAC) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Functional Description 40.4.1 Memory Interface 40.4.1.1 FIFO 40.4.1.2 Receive Buffers 40.4.1.3 Transmit Buffer 40.4.2 Transmit Block 40.4.3 Pause Frame Support 40.4.4 Receive Block 40.4.5 Address Checking Block 40.4.6 Broadcast Address 40.4.7 Hash Addressing 40.4.8 Copy All Frames (or Promiscuous Mode) 40.4.9 Type ID Checking 40.4.10 VLAN Support 40.4.11 PHY Maintenance 40.4.12 Media Independent Interface 40.4.12.1 RMII Transmit and Receive Operation 40.5 Programming Interface 40.5.1 Initialization 40.5.1.1 Configuration 40.5.1.2 Receive Buffer List 40.5.1.3 Transmit Buffer List 40.5.1.4 Address Matching 40.5.1.5 Interrupts 40.5.1.6 Transmitting Frames 40.5.1.7 Receiving Frames 40.6 Ethernet MAC 10/100 (EMAC) User Interface 40.6.1 Network Control Register 40.6.2 Network Configuration Register 40.6.3 Network Status Register 40.6.4 Transmit Status Register 40.6.5 Receive Buffer Queue Pointer Register 40.6.6 Transmit Buffer Queue Pointer Register 40.6.7 Receive Status Register 40.6.8 Interrupt Status Register 40.6.9 Interrupt Enable Register 40.6.10 Interrupt Disable Register 40.6.11 Interrupt Mask Register 40.6.12 PHY Maintenance Register 40.6.13 Pause Time Register 40.6.14 Hash Register Bottom 40.6.15 Hash Register Top 40.6.16 Specific Address 1 Bottom Register 40.6.17 Specific Address 1 Top Register 40.6.18 Specific Address 2 Bottom Register 40.6.19 Specific Address 2 Top Register 40.6.20 Specific Address 3 Bottom Register 40.6.21 Specific Address 3 Top Register 40.6.22 Specific Address 4 Bottom Register 40.6.23 Specific Address 4 Top Register 40.6.24 Type ID Checking Register 40.6.25 User Input/Output Register 40.6.26 EMAC Statistic Registers 40.6.26.1 Pause Frames Received Register 40.6.26.2 Frames Transmitted OK Register 40.6.26.3 Single Collision Frames Register 40.6.26.4 Multicollision Frames Register 40.6.26.5 Frames Received OK Register 40.6.26.6 Frames Check Sequence Errors Register 40.6.26.7 Alignment Errors Register 40.6.26.8 Deferred Transmission Frames Register 40.6.26.9 Late Collisions Register 40.6.26.10 Excessive Collisions Register 40.6.26.11 Transmit Underrun Errors Register 40.6.26.12 Carrier Sense Errors Register 40.6.26.13 Receive Resource Errors Register 40.6.26.14 Receive Overrun Errors Register 40.6.26.15 Receive Symbol Errors Register 40.6.26.16 Excessive Length Errors Register 40.6.26.17 Receive Jabbers Register 40.6.26.18 Undersize Frames Register 40.6.26.19 SQE Test Errors Register 40.6.26.20 Received Length Field Mismatch Register 41. USB Host Port (UHP) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Product Dependencies 41.4.1 I/O Lines 41.4.2 Power Management 41.4.3 Interrupt 41.5 Functional Description 41.5.1 Host Controller Interface 41.5.2 Host Controller Driver 41.6 Typical Connection 42. USB Device Port (UDP) 42.1 Overview 42.2 Block Diagram 42.3 Product Dependencies 42.3.1 I/O Lines 42.3.2 Power Management 42.3.3 Interrupt 42.4 Typical Connection 42.4.1 USB Device Transceiver 42.4.2 VBUS Monitoring 42.5 Functional Description 42.5.1 USB V2.0 Full-speed Introduction 42.5.1.1 USB V2.0 Full-speed Transfer Types 42.5.1.2 USB Bus Transactions 42.5.1.3 USB Transfer Event Definitions 42.5.2 Handling Transactions with USB V2.0 Device Peripheral 42.5.2.1 Setup Transaction 42.5.2.2 Data IN Transaction 42.5.2.3 Using Endpoints Without Ping-pong Attributes 42.5.2.4 Using Endpoints With Ping-pong Attribute 42.5.2.5 Data OUT Transaction 42.5.2.6 Data OUT Transaction Without Ping-pong Attributes 42.5.2.7 Using Endpoints With Ping-pong Attributes 42.5.2.8 Stall Handshake 42.5.2.9 Transmit Data Cancellation 42.5.2.10 Endpoints Without Dual-Banks 42.5.2.11 Endpoints With Dual-Banks 42.5.3 Controlling Device States 42.5.3.1 Not Powered State 42.5.3.2 Entering Attached State 42.5.3.3 From Powered State to Default State 42.5.3.4 From Default State to Address State 42.5.3.5 From Address State to Configured State 42.5.3.6 Entering in Suspend State 42.5.3.7 Receiving a Host Resume 42.5.3.8 Sending a Device Remote Wakeup 42.6 USB Device Port (UDP) User Interface 42.6.1 UDP Frame Number Register 42.6.2 UDP Global State Register 42.6.3 UDP Function Address Register 42.6.4 UDP Interrupt Enable Register 42.6.5 UDP Interrupt Disable Register 42.6.6 UDP Interrupt Mask Register 42.6.7 UDP Interrupt Status Register 42.6.8 UDP Interrupt Clear Register 42.6.9 UDP Reset Endpoint Register 42.6.10 UDP Endpoint Control and Status Register 42.6.11 UDP FIFO Data Register 42.6.12 UDP Transceiver Control Register 43. LCD Controller (LCDC) 43.1 Overview 43.2 Block Diagram 43.3 I/O Lines Description 43.4 Product Dependencies 43.4.1 I/O Lines 43.4.2 Power Management 43.4.3 Interrupt Sources 43.5 Functional Description 43.5.1 DMA Controller 43.5.1.1 Configuration Block 43.5.1.2 AHB Interface 43.5.1.3 Channel-U 43.5.1.4 Channel-L 43.5.1.5 Control 43.5.2 LCD Controller Core 43.5.2.1 Configuration Block 43.5.2.2 Datapath 43.5.2.3 FIFO 43.5.2.4 Serializer 43.5.2.5 Palette 43.5.2.6 Dithering 43.5.2.7 Shifter 43.5.2.8 Time Generator 43.5.2.9 Equation 1 43.5.2.10 Display 43.5.2.11 PWM 43.5.3 LCD Interface 43.6 Interrupts 43.7 Configuration Sequence 43.8 Double-buffer Technique 43.9 2D Memory Addressing 43.10 Register Configuration Guide 43.10.1 STN Mode Example 43.10.2 TFT Mode Example 43.11 LCD Controller (LCDC) User Interface 43.11.1 DMA Base Address Register 1 43.11.2 DMA Base Address Register 2 43.11.3 DMA Frame Pointer Register 1 43.11.4 DMA Frame Pointer Register 2 43.11.5 DMA Frame Address Register 1 43.11.6 DMA Frame Address Register 2 43.11.7 DMA Frame Configuration Register 43.11.8 DMA Control Register 43.11.9 LCD DMA 2D Addressing Register 43.11.10 LCD Control Register 1 43.11.11 LCD Control Register 2 43.11.12 LCD Timing Configuration Register 1 43.11.13 LCD Timing Configuration Register 2 43.11.14 LCD Frame Configuration Register 43.11.15 LCD FIFO Register 43.11.16 Dithering Pattern DP1_2 Register 43.11.17 Dithering Pattern DP4_7 Register 43.11.18 Dithering Pattern DP3_5 Register 43.11.19 Dithering Pattern DP2_3 Register 43.11.20 Dithering Pattern DP5_7 Register 43.11.21 Dithering Pattern DP3_4 Register 43.11.22 Dithering Pattern DP4_5 Register 43.11.23 Dithering Pattern DP6_7 Register 43.11.24 Power Control Register 43.11.25 Contrast Control Register 43.11.26 Contrast Value Register 43.11.27 LCD Interrupt Enable Register 43.11.28 LCD Interrupt Disable Register 43.11.29 LCD Interrupt Mask Register 43.11.30 LCD Interrupt Status Register 43.11.31 LCD Interrupt Clear Register 43.11.32 LCD Interrupt Test Register 43.11.33 LCD Interrupt Raw Status Register 44. Two D Graphics Controller (TDGC) 44.1 Description 44.2 Block Diagram 44.3 Functional Description 44.3.1 Hardware Acceleration 44.3.1.1 Line Draw 44.3.1.2 Line Draw Modes Absolute Line Draw Relative Line Draw 44.3.1.3 Relative Line Draw with Update XY Option 44.3.1.4 1D Line Draw with Broken Pattern 0xAAAA 44.3.1.5 2D Line Draw with Broken Pattern 0xEBBB 44.3.1.6 Block Transfer 44.3.1.7 Absolute Block Transfer 44.3.1.8 Relative Block Transfer 44.3.1.9 Block Transfer with Update X/Y 44.3.1.10 Clipping 44.3.1.11 Draw Command Queuing 44.3.1.12 Recommended Procedure for Using the Command Queue 44.3.1.13 Procedure to Switch from Command Queue Drawing to Direct Drawing 44.3.2 Video RAM 44.4 Examples of Drawing Functions 44.4.1 Line Draw 44.4.2 Block Transfer 44.4.3 Clipped Line Draw 44.4.4 Drawing Using Command Queue 44.5 Two D Graphic Controller (TDGC) User Interface 44.5.1 Block Transfer Size X Register 44.5.2 Block Transfer Size Y Register 44.5.3 Source/Begin X Register 44.5.4 Source/Begin Y Register 44.5.5 Target/End X Register 44.5.6 Target/End Y Register 44.5.7 Line Width Register 44.5.8 Line Pattern Register 44.5.9 Color Select Register 44.5.10 Logic Operation Register 44.5.11 Graphics Operation Register 44.5.12 Extended Begin X Register 44.5.13 Extended Begin Y Register 44.5.14 Extended End X Register 44.5.15 Extended End Y Register 44.5.16 Extended Color Select Register 44.5.17 Clip Control Register 44.5.18 Clip Rectangle Minimum X Register 44.5.19 Clip Rectangle Maximum X Register 44.5.20 Clip Rectangle Minimum Y Register 44.5.21 Clip Rectangle Maximum Y Register 44.5.22 Graphics Status Register 44.5.23 VRAM Size Register 44.5.24 Graphics Interrupt Register 44.5.25 Graphics Interrupt Mask Register 44.5.26 Bits Per Pixel Register 44.5.27 Command Queue Count Register 44.5.28 Command Queue Status Register 44.5.29 Command Queue Register 44.5.30 VRAM OFFSET Register 44.5.31 DATA Format Register 45. Image Sensor Interface (ISI) 45.1 Overview 45.2 Block Diagram 45.3 Functional Description 45.3.1 Data Timing 45.3.2 Data Ordering 45.3.3 Clocks 45.3.4 Preview Path 45.3.4.1 Scaling, Decimation (Subsampling) 45.3.4.2 Color Space Conversion 45.3.4.3 Memory Interface 45.3.4.4 FIFO and DMA Features 45.3.4.5 Example 45.3.5 Codec Path 45.3.5.1 Color Space Conversion 45.3.5.2 Memory Interface 45.3.5.3 DMA Features 45.4 Image Sensor Interface (ISI) User Interface 45.4.1 ISI Control 1 Register 45.4.2 ISI Control 2 Register 45.4.3 ISI Status Register 45.4.4 Interrupt Enable Register 45.4.5 ISI Interrupt Disable Register 45.4.6 ISI Interrupt Mask Register 45.4.7 ISI Preview Register 45.4.8 ISI Preview Decimation Factor Register 45.4.9 ISI Preview Primary FBD Register 45.4.10 ISI Codec DMA Base Address Register 45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register 45.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register 45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register 45.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register 45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register 46. SAM9263 Electrical Characteristics 46.1 Absolute Maximum Ratings 46.2 DC Characteristics 46.3 Power Consumption 46.3.1 Power Consumption versus Modes 46.4 Core Power Supply POR Characteristics 46.5 Clock Characteristics 46.5.1 Processor Clock Characteristics 46.5.2 Master Clock Characteristics 46.5.3 XIN Clock Characteristics 46.6 Crystal Oscillator Characteristics 46.6.1 32 kHz Oscillator Characteristics 46.6.2 32 kHz Crystal Characteristics 46.6.3 Main Oscillator Characteristics 46.6.4 Crystal Characteristics 46.6.5 PLL Characteristics 46.7 I/Os 46.8 USB Transceiver Characteristics 46.9 EBI Timings 46.9.1 SMC Timing Conditions 46.9.2 EBI 0 Timings 46.9.2.1 Read Timings 46.9.2.2 Write Timings 46.9.3 EBI 1 Timings 46.9.3.1 Read Timings 46.9.3.2 Write Timings 46.9.4 SDRAMC Signals 46.9.4.1 External Bus Interface 0 Timings 46.9.4.2 External Bus Interface 1 Timings 46.10 EMAC Timings 46.10.1 MII Mode 46.10.2 RMII Mode 46.11 Peripheral Timings 46.11.1 SPI 46.11.1.1 Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode 46.11.1.2 Timing Conditions 46.11.1.3 Timing Extraction 46.11.2 ISI 46.11.3 MCI 46.11.4 UDP and UHP Switching Characteristics 47. SAM9263 Mechanical Characteristics 47.1 Package Drawing AT91SAM9263B-CU 47.1.1 Soldering Profile 47.2 Package Drawing AT91SAM9263B-CU-100 47.2.1 Soldering Profile 48. Marking 49. SAM9263 Ordering Information 50. SAM9263 Errata 50.1 SAM9263 Errata - Revision “B” Parts 50.1.1 Main Oscillator 50.1.1.1 Main Oscillator: Spurious Malfunction of Main Oscillator 50.1.2 Two D Graphic Controller (TDGC) 50.1.2.1 Polygon Fill Function 50.1.2.2 TDGC Clipping Function 50.1.3 AC97 50.1.3.1 Bad Management of Endianness Conversion 50.1.4 Bus Matrix 50.1.4.1 Problem with Locked Transfers 50.1.5 CAN 50.1.5.1 CAN: Low Power Mode and Error Frame 50.1.5.2 CAN: Low Power Mode and Pending Transmit Messages 50.1.5.3 CAN: Contents of Mailbox 0 can be sent Even if Mailbox is Disabled 50.1.6 ECC 50.1.6.1 ECC status may be wrong with external SRAM 50.1.7 EMACB 50.1.7.1 Transmit Underrun Errors 50.1.8 LCD 50.1.8.1 LCD Screen Shifting After a Reset 50.1.8.2 LCD Periodic Bad Pixels 50.1.8.3 24-bit Packed Mode 50.1.9 MCI 50.1.9.1 Busy signal of R1b responses is not taken in account 50.1.9.2 SDIO interrupt does not work with slots other than A 50.1.9.3 Data Timeout Error Flag 50.1.9.4 Data Write Operation and Number of Bytes 50.1.9.5 Flag Reset is not correct in half duplex mode 50.1.10 NTRST 50.1.10.1 NTRST: Device does not boot correctly due to power-up sequencing issue 50.1.11 Reset Controller (RSTC) 50.1.11.1 RSTC: ERSTL Default Value is 1 50.1.11.2 RSTC: Reset during SDRAM Accesses 50.1.12 SDRAM Controller 50.1.12.1 Mobile SDRAM Device Initialization Constraint 50.1.13 Static Memory Controller (SMC) 50.1.13.1 SMC Chip Select Parameters Modification 50.1.14 Serial Peripheral Interface (SPI) 50.1.14.1 SPI: Pulse Generation on SPCK 50.1.14.2 SPI: Bad PDC Behavior when CSAAT = 1 and SCBR = 1 50.1.14.3 SPI: LASTXFER (Last Transfer) Behavior 50.1.14.4 SPI: Baudrate Set to 1 50.1.14.5 SPI: Software Reset 50.1.14.6 SPI: SPI Software Reset Must Be Written Twice 50.1.14.7 SPI: Chip Select and Fixed Mode 50.1.14.8 SPI: Software Reset Must be Written Twice 50.1.15 Serial Synchronous Controller (SSC) 50.1.15.1 Transmitter Limitations in Slave Mode 50.1.15.2 Periodic Transmission Limitations in Master Mode 50.1.15.3 Unexpected Delay on TD output 50.1.16 Pulse Width Modulation (PWM) 50.1.16.1 Zero Period 50.1.17 System Controller 50.1.17.1 Possible Event Loss when Reading RTT_SR 50.1.18 Two-wire Interface (TWI) 50.1.18.1 Clock Divider 50.1.18.2 Disabling Does Not Operate Correctly 50.1.18.3 Software Reset 50.1.18.4 STOP not Generated 50.1.19 UDP 50.1.19.1 Bad Data in the First IN Data Stage 50.1.20 UHP 50.1.20.1 Non-ISO IN Transfers 50.1.20.2 ISO OUT Transfers 50.1.20.3 Remote Wakeup Event 50.1.21 USART 50.1.21.1 RXBRK Flag Error in Asynchronous Mode 50.1.21.2 RTS not Expected Behavior 50.1.21.3 Two characters sent if CTS rises during emission 50.1.21.4 TXD signal is floating in Modem and Hardware Handshaking mod 50.1.21.5 DCD is Active High instead of Low 50.1.21.6 Bad value in Number of Errors Register 51. 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