Datasheet MAX4684, MAX4685 (Maxim) - 7

MAX4684/MAX4685 0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSP
Detailed Description
supply voltages. Maximum supply voltage (V+) must not The MAX4684/MAX4685 are low on-resistance, low- exceed +6V. Protection diode D1 also protects against voltage, dual SPDT analog switches that operate from a some overvoltage situations. No damage will result on +1.8V to +5.5V supply. The devices are fully specified for Figure 1’s circuit if the supply voltage is below the abso- nominal 3V applications. The MAX4684/MAX4685 have lute maximum rating applied to an analog signal pin. break-before-make switching and fast switching speeds
UCSP Package Consideration
(tON = 50ns max, tOFF = 40ns max). For general UCSP package information and PC layout The MAX4684 offers asymmetrical normally closed (NC) considerations, please refer to the Maxim Application and normally open (NO) RON for applications that require Note (Wafer-Level Ultra-Chip-Board-Scale Package). asymmetrical loads (examples include speaker headsets and internal speakers). The part features a 0.5Ω max
UCSP Reliability
RON for its NC switch and a 0.8Ω max RON for its NO The chip-scale package (UCSP) represents a unique switch at the 2.7V supply. The MAX4685 features a 0.8Ω packaging form factor that may not perform equally to a max on-resistance for both NO and NC switches at the packaged product through traditional mechanical reliabil- +2.7V supply. ity tests. UCSP reliability is integrally linked to the user’s
Applications Information
assembly methods, circuit board material, and usage environment. The user should closely review these areas
Digital Control Inputs
when considering use of a UCSP package. Performance The MAX4684/MAX4685 logic inputs accept up to +5.5V through Operating Life Test and Moisture Resistance regardless of supply voltage. For example, with a +3.3V remains uncompromised as it is primarily determined by supply, IN_ may be driven low to GND and high to 5.5V. the wafer-fabrication process. Driving IN_ rail-to-rail minimizes power consumption. Mechanical stress performance is a greater consideration Logic levels for a +1.8V supply are 0.5V (low) and 1.4V for a UCSP package. UCSPs are attached through direct (high). solder contact to the user’s PC board, foregoing the inher-
Analog Signal Levels
ent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Analog signals that range over the entire supply voltage Maxim’s qualification plan, test data, and recommendations (V+ to GND) are passed with very little change in on- are detailed in the UCSP application note, which can be resistance (see Typical Operating Characteristics). The found on Maxim’s website at
www.maximintegrated.com
. switches are bidirectional, so the NO_, NC_, and COM_ pins can be either inputs or outputs. POSITIVE SUPPLY
Power-Supply Sequencing and Overvoltage Protection
D1 V+
Caution: Do not exceed the absolute maximum rat- MAX4684 ings because stresses beyond the listed ratings may MAX4685 cause permanent damage to devices.
Proper power-supply sequencing is recommended for all NO COM CMOS devices. Always apply V+ before applying analog Vg signals, especially if the analog signal is not current lim- ited. If this sequencing is not possible, and if the analog inputs are not current limited to <20mA, add a small sig- GND nal diode (D1) as shown in Figure 1. Adding a protection diode reduces the analog range to a diode drop (about Figure 1. Overvoltage Protection Using Two External Blocking 0.7V) below V+ (for D1). RON increases slightly at low Diodes www.maximintegrated.com Maxim Integrated │ 7