Datasheet ADP1864 (Analog Devices) - 8

ADP1864 Data Sheet THEORY OF OPERATION
The ADP1864 is a constant frequency (580 kHz), current-mode positive input to the error amplifier is driven by a 0.8 V band buck controller. PGATE drives the gate of the external P-channel gap reference. An increase in the load current causes a small FET. The duty cycle of the external FET dictates the output drop in the feedback voltage, in turn causing an increase in the voltage and the current supplied to the load. COMP voltage and, therefore, the duty cycle. The resulting increase in the on time of the FET provides the additional The peak inductor current is measured across the external sense current required by the load. resistor, while the system output voltage is fed back through an external resistor divider to the FB pin.
LOOP STARTUP
At the start of every oscil ator cycle, PGATE turns on the Pulling the COMP pin to GND disables the ADP1864. When external FET, causing the inductor current, and therefore the the COMP pin is released from GND, an internal 0.6 μA current current sense amplifier voltage, to increase. The inductor source charges the external compensation capacitor on the current increases until the current amplifier voltage equals COMP node. Once the COMP voltage has charged to 0.67 V, the voltage at the COMP pin. This resets the internal flip-flop, the internal control blocks are enabled and COMP is pulled up causing PGATE to go high and turning off the external FET. to its minimum normal operating voltage (0.9 V). As the voltage at The inductor current decreases until the beginning of the next COMP continues to increase, the on time of the external FET oscil ator period. increases to supply the required inductor current. The loop stabilizes completely once the COMP voltage is sufficiently high The voltage at the COMP node is the output of the internal to support the load current. The regulation voltage at FB is 0.8 V. error amplifier. The negative input of the error amplifier is the output voltage scaled by an external resistive divider, and the
VIN = 3.15V TO 14V IN CS 5 4 V 15mV ICMP IN VREF UVLO, 0.8V SWITCHING VREF RSI SLOPE LOGIC AND S 6 COMP R BLANKING Q UVLO OSC CIRCUIT G S D 2.5V PGATE 2A GND FREQUENCY OVP 2 FOLDBACK 0.35V V VREF IN SHORT-CIRCUIT + DETECT 80mV EAMP VREF 0.8V FB 0.6µA 3 VIN 0.3V SHDN 0.3V SHDN CMP UV COMP 1 UVLO 0.8V ADP1864
013 05562- Figure 12. Functional Block Diagram Rev. C | Page 8 of 16 Document Outline Features Applications General Description Typical Applications Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Loop Startup Short-Circuit Protection Undervoltage Lockout (UVLO) Overvoltage Lockout Protection (OVP) Soft Start Applications Information ADIsimPower Design Tool Duty Cycle Ripple Current Sense Resistor Inductor Value MOSFET Diode Input Capacitor Output Capacitor Feedback Resistors Layout Considerations Example Applications Circuits Outline Dimensions Ordering Guide