Datasheet ADP1828 (Analog Devices) - 8

ADP1828 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS T U T E FREQ 1 20 CLKOUT C Q O S N E K K T SYNC 2 19 CLKSET Y R L L S S F C C B EN 3 0 9 8 7 6 18 BST 2 1 1 1 1 ADP1828 IN 4 17 DH TOP VIEW VREG 5 (Not to Scale) 16 SW EN 1 ADP1828 15 DH GND 6 15 CSL IN 2 14 SW VREG 3 13 CSL COMP 7 14 PGND TOP GND 4 VIEW 12 PGND FB 8 13 DL COMP 5 11 DL TRK 9 12 PV SS
004
10 11 PGOOD 6 7 8 9 0 (Not to Scale) 1
06865-
B K S D V F R S O P T O G P
59
NOTES
0
1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE.
06865- Figure 3. 20-Lead QSOP Pin Configuration Figure 4. 20-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions QSOP LSCSP Pin No. Pin No. Mnemonic Description
1 19 FREQ Frequency Control Input. Low for 300 kHz, high for 600 kHz, or connect a resistor from FREQ to GND to set the free-running frequency between 300 kHz and 600 kHz. 2 20 SYNC Frequency Synchronization Input. Accepts external signals between 300 kHz and 600 kHz if FREQ is set to low, or between 600 kHz and 1.2 MHz if FREQ is set to high. If fOSC is set by RFREQ, then the synchronization frequency range is from fOSC up to 600 kHz. If SYNC is not used, connect SYNC to GND or VREG. VSYNC can be driven up to 6 V even when VIN is less than 6 V. 3 1 EN Enable Input. Drive EN high or tristate EN to turn on the ADP1828 controller, and drive it low to turn off. Connect EN to IN for automatic startup. 4 2 IN Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1828 from LDO, VREG; tie PV to VREG. For input voltages between 3 V and 5.5 V, tie IN, PV, and VREG together. 5 3 VREG Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG. Bypass VREG to AGND plane with 1 μF ceramic capacitor for stable operation, for example, a 10 V X5R 1 μF ceramic capacitor is sufficient. The VREG output is 5 V when IN = 5 V + dropout. Connect IN to VREG and PV when IN = 3 V to 5.5 V. For applications with IN < 5.5 V and IN not connected to VREG, keep in mind that VREG = VIN – dropout. VREG needs to be ≥3 V for proper operation. 6 4 GND Ground for Internal Circuits. Tie the bottom of the feedback dividers to this GND. 7 5 COMP Error Amplifier Output. Connect an RC network from COMP to FB for loop compensation. 8 6 FB Voltage Feedback. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB to set the output voltage. 9 7 TRK Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If the tracking function is not used, connect TRK to VREG. 10 8 SS Soft Start Control Input. Connect a capacitor from SS to GND to set the soft start period. 11 9 PGOOD Open-Drain Power-Good Output. Sinks current when FB is out of regulation. Connect a pull-up resistor from PGOOD to VREG. 12 10 PV Positive Input Voltage for Gate Driver DL. When IN is 3 V to 5.5 V, connect IN to VREG and PV. Connect a 1 μF bypass capacitor from PV to PGND. When IN = 5.5 V to 20 V, connect PV to VREG. 13 11 DL Low-Side (Synchronous Rectifier) Gate Driver Output. 14 12 PGND Power GND. Ground for gate driver. 15 13 CSL Current Sense Comparator Inverting Input. Connect a resistor between CSL and SW to set the current- limit offset. 16 14 SW Switch Node Connection. 17 15 DH High-Side (Switch) Gate Driver Output. 18 16 BST Boost Capacitor Input. Powers the high-side gate driver DH. Connect a 0.22 μF to 0.47 μF ceramic capacitor from BST to SW and a Schottky diode from PV to BST. Rev. E | Page 8 of 33 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT POWER INTERNAL LINEAR REGULATOR SOFT START ERROR AMPLIFIER CURRENT-LIMIT SCHEME MOSFET DRIVERS SETTING THE OUTPUT VOLTAGE SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION COMPENSATION POWER-GOOD INDICATOR THERMAL SHUTDOWN SHUTDOWN CONTROL TRACKING APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR OUTPUT LC FILTER SELECTING THE MOSFETS SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SOFT START SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING COINCIDENT TRACKING RATIOMETRIC TRACKING THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINE RECOMMENDED COMPONENT MANUFACTURERS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE