Datasheet PIC16F84A (Microchip) - 8

link to page 36
PIC16F84A
2.3.1 STATUS REGISTER
Note 1:
The IRP and RP1 bits (STATUS<7:6>) The STATUS register contains the arithmetic status of are not used by the PIC16F84A and the ALU, the RESET status and the bank select bit for should be programmed as cleared. Use of data memory. these bits as general purpose R/W bits is NOT recommended, since this may affect As with any register, the STATUS register can be the upward compatibility with future products. destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC
2:
The C and DC bits operate as a borrow or C bits, then the write to these three bits is disabled. and digit borrow out bit, respectively, in These bits are set or cleared according to device logic. subtraction. See the SUBLW and SUBWF Furthermore, the TO and PD bits are not writable. instructions for examples. Therefore, the result of an instruction with the STATUS
3:
When the STATUS register is the register as destination may be different than intended. destination for an instruction that affects For example, CLRF STATUS will clear the upper three the Z, DC or C bits, then the write to these bits and set the Z bit. This leaves the STATUS register three bits is disabled. The specified bit(s) as 000u u1uu (where u = unchanged). will be updated according to device logic Only the BCF, BSF, SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 7-2), because these instructions do not affect any status bit.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7-6
Unimplemented:
Maintain as ‘0’ bit 5
RP0
: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4
TO
: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3
PD
: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2
Z
: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1
DC
: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0
C
: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred
Note:
A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS35007C-page 8  2001-2013 Microchip Technology Inc. Document Outline 1.0 Device Overview FIGURE 1-1: PIC16F84A Block Diagram TABLE 1-1: PIC16F84A Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: Program Memory Map and Stack - PIC16F84A 2.2 Data Memory Organization 2.2.1 General purpose Register File FIGURE 2-2: Register File Map - PIC16F84A 2.3 Special Function Registers TABLE 2-1: Special Function Register File Summary 2.3.1 STATUS Register Register 2-1: Status Register (Address 03h, 83h) 2.3.2 OPTION Register Register 2-2: OPTION Register (Address 81h) 2.3.3 INTCOn Register Register 2-3: INTCON Register (Address 0Bh, 8Bh) 2.4 PCL and PCLATH 2.4.1 Stack 2.5 Indirect Addressing; INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing EXAMPLE 2-2: How to Clear RAM Using Indirect Addressing FIGURE 2-3: Direct/Indirect Addressing 3.0 Data EEPROM Memory Register 3-1: EECON1 Register (Address 88h) 3.1 Reading the EEPROM Data Memory EXAMPLE 3-1: Data EEPROM Read 3.2 Writing to the EEPROM Data Memory EXAMPLE 3-2: Data EEPROM Write 3.3 Write Verify EXAMPLE 3-3: Write Verify TABLE 3-1: Registers/Bits Associated with Data EEPROM 4.0 I/O Ports 4.1 PORTA and TRISA Registers EXAMPLE 4-1: Initializing PORTA FIGURE 4-1: Block Diagram of Pins RA3:RA0 FIGURE 4-2: Block Diagram of Pin RA4 TABLE 4-1: PORTA Functions TABLE 4-2: Summary of Registers Associated With PORTA 4.2 PORTB and TRISB Registers EXAMPLE 4-2: Initializing PORTB FIGURE 4-3: Block Diagram of Pins RB7:RB4 FIGURE 4-4: Block Diagram of Pins RB3:RB0 TABLE 4-3: PORTB Functions TABLE 4-4: Summary of Registers Associated With PORTB 5.0 Timer0 Module 5.1 Timer0 Operation 5.2 Prescaler FIGURE 5-1: Timer0 Block Diagram 5.2.1 Switching Prescaler ASSIGnment 5.3 Timer0 Interrupt FIGURE 5-2: Block Diagram of the Timer0/WDT Prescaler TABLE 5-1: Registers Associated with Timer0 6.0 Special Features of the CPU 6.1 Configuration Bits Register 6-1: PIC16F84A Configuration Word 6.2 Oscillator Configurations 6.2.1 Oscillator Types 6.2.2 Crystal Oscillator/CERAmic Resonators FIGURE 6-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) FIGURE 6-2: External Clock Input Operation (HS, XT or LP OSC Configuration) TABLE 6-1: Capacitor Selection for Ceramic Resonators TABLE 6-2: Capacitor Selection for Crystal Oscillator 6.2.3 RC Oscillator FIGURE 6-3: RC Oscillator Mode 6.3 Reset FIGURE 6-4: Simplified Block Diagram of On-Chip Reset Circuit TABLE 6-3: Reset Condition for Program Counter and the STATUS Register TABLE 6-4: Reset Conditions for All Registers 6.4 Power-on Reset (POR) 6.5 Power-up Timer (PWRT) 6.6 Oscillator Start-up Timer (OST) FIGURE 6-5: External Power-on Reset Circuit (For Slow Vdd Power-up) FIGURE 6-6: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1 FIGURE 6-7: Time-out Sequence on Power-up (MCLR Not Tied To Vdd): Case 2 FIGURE 6-8: Time-out Sequence on Power-up (MCLR Tied to Vdd): Fast Vdd Rise Time FIGURE 6-9: Time-Out Sequence on Power-Up (MCLR Tied to Vdd): Slow Vdd Rise Time 6.7 Time-out Sequence and Power-down Status Bits (TO/PD) TABLE 6-5: Time-out in Various Situations TABLE 6-6: STATUS bits and Their Significance 6.8 Interrupts FIGURE 6-10: Interrupt Logic 6.8.1 INT Interrupt 6.8.2 TMR0 Interrupt 6.8.3 PORTB Interrupt 6.8.4 Data EEPROM Interrupt 6.9 Context Saving During Interrupts EXAMPLE 6-1: Saving STATUS and W Registers in RAM 6.10 Watchdog Timer (WDT) 6.10.1 WDT Period 6.10.2 WDT Programming Considerations FIGURE 6-11: Watchdog Timer Block Diagram TABLE 6-7: Summary of Registers Associated With the Watchdog Timer 6.11 Power-down Mode (SLEEP) 6.11.1 SLEEP 6.11.2 Wake-up from SLEEP FIGURE 6-12: Wake-up From Sleep Through Interrupt 6.11.3 Wake-Up Using Interrupts 6.12 Program Verification/Code Protection 6.13 ID Locations 6.14 In-Circuit Serial Programming 7.0 Instruction Set Summary TABLE 7-1: Opcode Field Descriptions FIGURE 7-1: General Format for Instructions TABLE 7-2: PIC16CXXX Instruction Set 7.1 Instruction Descriptions 8.0 Development Support 9.0 Electrical Characteristics FIGURE 9-1: PIC16F84A-20 Voltage-Frequency Graph FIGURE 9-2: PIC16LF84A-04 Voltage- Frequency Graph FIGURE 9-3: PIC16F84A-04 Voltage- Frequency Graph 9.1 DC Characteristics 9.2 DC Characteristics: PIC16F84A-04 (Commercial, Industrial) PIC16F84A-20 (Commercial, Industrial) PIC16LF84A-04 (Commercial, Industrial) 9.3 AC (Timing) Characteristics 9.3.1 Timing Parameter Symbology 9.3.2 Timing Conditions TABLE 9-1: Temperature and Voltage Specifications - AC FIGURE 9-4: Parameter Measurement Information FIGURE 9-5: Load Conditions 9.3.3 Timing Diagrams and Specifications FIGURE 9-6: External Clock Timing TABLE 9-2: External Clock Timing Requirements FIGURE 9-7: CLKOUT and I/O Timing TABLE 9-3: CLKOUT and I/O Timing Requirements FIGURE 9-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing TABLE 9-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements FIGURE 9-9: Timer0 Clock Timings TABLE 9-5: Timer0 Clock Requirements 10.0 DC/AC Characteristic Graphs FIGURE 10-1: Typical Idd vs. Fosc OVER Vdd (HS Mode, 25°C) FIGURE 10-2: Maximum Idd vs. Fosc OVER Vdd (HS Mode, -40° to +125°C) FIGURE 10-3: Typical Idd vs. Fosc OVER Vdd (XT Mode, 25°C) FIGURE 10-4: Maximum Idd vs. Fosc OVER Vdd (XT Mode, -40° to +125°C) FIGURE 10-5: Typical Idd vs. Fosc OVER Vdd (LP Mode, 25°C) FIGURE 10-6: Maximum Idd vs. Fosc OVER Vdd (LP Mode, -40° to +125°C) FIGURE 10-7: Average Fosc vs. Vdd for R (RC Mode, C = 22 pF, 25°C) FIGURE 10-8: Average Fosc vs. Vdd for R (RC Mode, C = 100 pF, 25°C) FIGURE 10-9: Average Fosc vs. Vdd for R (RC Mode, C = 300 pF, 25°C) FIGURE 10-10: Ipd vs. Vdd (Sleep Mode, all peripherals disabled) FIGURE 10-11: Ipd vs. Vdd (WDT Mode) FIGURE 10-12: Typical, Minimum, and Maximum WDT Period vs. Vdd over Temp FIGURE 10-13: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40°C to +125°C) FIGURE 10-14: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40°C to +125°C) FIGURE 10-15: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 5V, -40°C to +125°C) FIGURE 10-16: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 3V, -40°C to +125°C) FIGURE 10-17: Minimum and Maximum Vin vs. Vdd, (TTL Input, -40°C to +125°C) FIGURE 10-18: Minimum and Maximum Vin vs. Vdd (ST Input, -40°C to +125°C) 11.0 Packaging Information 11.1 Package Marking Information Appendix A: Revision History Appendix B: Conversion Considerations Appendix C: Migration from Baseline to Mid-range Devices A B C D E F I M O P R S T W Z The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Indianapolis Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service