OP285+15VMeasuring Settling Time0.1F The design of OP285 combines high slew rate and wide gain- 38+ bandwidth product to produce a fast-settling (ts < l µs) amplifier 11/2+ 7A13 PLUG-INOP285 for 8- and 12-bit applications. The test circuit designed to measure 20.1F– the settling time of the OP285 is shown in Figure 7. This test 4 method has advantages over false-sum node techniques in that *–15V the actual output of the amplifier is measured, instead of an –7A13 PLUG-IN error voltage at the sum node. Common-mode settling effects are exercised in this circuit in addition to the slew rate and 300pF1k bandwidth effects measured by the false-sum-node method. Of 15V|VIREF|OUT course, a reasonably flat-top pulse is required as the stimulus. TTL1kINPUT1.5k2N3904 The output waveform of the OP285 under test is clamped by Schottky diodes and buffered by the JFET source follower. 1N41482N290710F+1k The signal is amplified by a factor of ten by the OP260 and 1.8k then Schottky-clamped at the output to prevent overloading 15V220 the oscilloscope’s input amplifier. The OP41 is configured as 0.47F a fast integrator which provides overall dc offset nulling. 0.1FHigh Speed Operation0.01F As with most high speed amplifiers, care should be taken with *NOTEVDECOUPLE CLOSEREF supply decoupling, lead dress, and component placement. Rec- TOGETHER ON GROUND PLAN(–1V)WITH SHORT LEAD LENGTHS. ommended circuit configurations for inverting and noninverting applications are shown in Figures 8 and Figure 9. Figure 5. Transient Output Load Current Test Fixture +15V10F+A1 1,2 VT138.9NS0.1F10090TTL CTRL(5V/ DIV)2 –81/21VOUT10VVOP285IN3 +VOUTR104L(2MV/ DIV) 0%15k5V2MV50NS0.1F10F Figure 6. OP285’s Output Load Current Recovery Time –15V Figure 8. Unity Gain Follower 16–20V–++15V1kOUTPUT0.1F(TO SCOPE)V+D3D4RL1kDUT2N44161/2 OP260AJV–D1D21F0.1FRF2k10k+–RGIC216–20V22210k5V2N2222A7501N414815kSCHOTTKY DIODES D1–D4 ARE HEWLETT-PACKARD HP5082-2835 IC1 IS 1/2 OP260AJ–15VIC2 IS PMI OP41EJ Figure 7. OP285’s Settling Time Test Fixture –8– REV. C