Datasheet MCP47CXBXX (Microchip) - 3

MCP47CXBXX MCP47CMBX2 Block Diagram (Dual Channel Output)
VDD
Memory
Power-up/Brown-out Control VSS VOLATILE (5x16) SDA DAC0 and DAC1 I2C Serial Interface Module V SCL REF and Control Logic POWER-DOWN (WiperLock™ Technology) GAIN STATUS A0 ADDR6:ADDR0 A1 NONVOLATILE (14x16) DAC0 and DAC1 V LAT0/HVC IHH VREF POWER-DOWN LAT0 GAIN/I2C ADDRESS WiperLock™ VDD PD1:PD0 and VREF1:VREF0 Band Gap VBG GAIN 1.214V VREF1:VREF0 OP AMP V V
(2)
OUT0 REF0 r VDD PD1:PD0 der sisto k Re Lad 1k 100 VREF1:VREF0 LAT1
(1)
LAT0
(1)
VDD PD1:PD0 and VREF1:VREF0 GAIN VBG VREF1:VREF0 OP AMP V
(2)
VOUT1 REF1 V r DD o PD1:PD0 st er si k 0 Re Ladd 1k 10 VREF1:VREF0
Note 1:
On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to LAT1 input of DAC1.
2:
On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to VREF1 input of DAC1.  2018-2019 Microchip Technology Inc. DS20006089B-page 3 Document Outline Features General Description Applications MCP47CMBX1 Block Diagram (Single-Channel Output) MCP47CMBX2 Block Diagram (Dual Channel Output) Family Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings(†) DC Characteristics DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Characteristics (Continued) DC Notes: 1.1 Timing Waveforms and Requirements 1.1.1 Wiper Settling Time FIGURE 1-1: VOUT Settling Time Waveforms. TABLE 1-1: Wiper Settling Timing 1.1.2 Latch Pin (LAT) Timing FIGURE 1-2: LAT Pin Waveforms. TABLE 1-2: LAT Pin Timing 1.2 I2C Mode Timing Waveforms and Requirements FIGURE 1-3: Power-on and Brown-out Reset Waveforms. FIGURE 1-4: I2C Power-Down Command Timing. TABLE 1-3: Reset Timing FIGURE 1-5: I2C Bus Start/Stop Bits and HVC Timing Waveforms. TABLE 1-4: I2C Bus Start/Stop Bits and LAT Requirements FIGURE 1-6: I2C Bus Data Timing Waveforms. TABLE 1-5: I2C Bus Requirements (Slave Mode) TABLE 1-5: I2C Bus Requirements (Slave Mode) (Continued) Timing Notes: Temperature Specifications 2.0 Typical Performance Curves 2.1 Electrical Data FIGURE 2-1: Average Device Supply Current vs. FSCL Frequency, Voltage and Temperature – Active Interface, VRxB:VRxA = 00, (VDD Mode). FIGURE 2-2: Average Device Supply Current vs. FSCL Frequency, Voltage and Temperature – Active Interface, VRxB:VRxA = 01 (Band Gap Mode). FIGURE 2-3: Average Device Supply Current vs. FSCL Frequency, Voltage and Temperature – Active Interface, VRxB:VRxA = 11 (VREF Buffered Mode). FIGURE 2-4: Average Device Supply Current – Inactive Interface (SCL = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = 00 (VDD Mode). FIGURE 2-5: Average Device Supply Current – Inactive Interface (SCL = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = 01 (Band Gap Mode). FIGURE 2-6: Average Device Supply Current – Inactive Interface (SCL = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = 11 (VREF Buffered Mode). FIGURE 2-7: Average Device Supply Current vs. FSCL Frequency, Voltage and Temperature – Active Interface, VRxB:VRxA = 10 (VREF Unbuffered Mode). FIGURE 2-8: Average Device Supply Active Current (IDDA) (at 5.5V and FSCL = 3.4 MHz) vs. Temperature and DAC Reference Voltage Mode. FIGURE 2-9: Average Device Supply Current – Inactive Interface (SCL = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = 10 (VREF Unbuffered Mode). 2.2 Linearity Data 2.2.1 Total Unadjusted Error (TUE) – MCP47CXB2X (12-Bit), VREF = VDD (VRXB:VRXA = 10), Gain = 1X, Code 64-4032 FIGURE 2-10: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V. FIGURE 2-11: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V. FIGURE 2-12: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V. FIGURE 2-13: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V. FIGURE 2-14: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V. FIGURE 2-15: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V. 2.2.2 Integral Nonlinearity (INL) – MCP47CXB2X (12-Bit), VREF = VDD (VRXB:VRXA = 10), Gain = 1X, Code 64-4032 FIGURE 2-16: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V. FIGURE 2-17: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V. FIGURE 2-18: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V. FIGURE 2-19: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V. FIGURE 2-20: INL Error vs. DAC Code and Temperature (Code 100-4000) (Dual Channel – MCP47CXB22), VDD = 2.7V. FIGURE 2-21: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V. 2.2.3 Differential Nonlinearity (DNL) – MCP47CXB2X (12-Bit), VREF = VDD (VRXB:VRXA = 10), Gain = 1X, Code 64-4032 FIGURE 2-22: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V. FIGURE 2-23: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V. FIGURE 2-24: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V. FIGURE 2-25: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V. FIGURE 2-26: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V. FIGURE 2-27: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V. 2.2.4 Total Unadjusted Error (TUE) – MCP47CXB2X (12-Bit), External VREF = 0.5 VDD (VRXB:VRXA = 10), Unbuffered, Code 64-4032 FIGURE 2-28: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VREF = 0.5 x VDD = 2.75V, Gain = 2x. FIGURE 2-29: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VREF = 0.5 x VDD = 1.35V, Gain = 2x. FIGURE 2-30: Total Unadjusted Error (VOUT) vs. DAC Code, and Temperature (Dual Channel – MCP47CXB22), VREF = 0.5 x VDD = 2.75V, Gain = 2x. FIGURE 2-31: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VREF = 0.5 x VDD = 1.35V, Gain = 2x. 2.2.5 Integral Nonlinearity (INL) – MCP47CXB2X (12-Bit), External VREF = 0.5 VDD (VRXB:VRXA = 10), Unbuffered, Code 64-4032 FIGURE 2-32: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VREF = 0.5 x VDD = 2.75V, Gain = 2x. FIGURE 2-33: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VREF = 0.5 x VDD = 1.35V, Gain = 2x. FIGURE 2-34: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VREF = 0.5 x VDD = 2.75V, Gain = 2x. FIGURE 2-35: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VREF = 0.5 x VDD = 1.35V, Gain = 2x. 2.2.6 Differential Nonlinearity Error (DNL) – MCP47CXB2X (12-Bit), External VREF = 0.5 VDD (VRXB:VRXA = 10), Unbuffered, Code 64-4032 FIGURE 2-36: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, VREF = 0.5 x VDD = 2.75V. FIGURE 2-37: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, VREF = 0.5 x VDD = 1.35V. FIGURE 2-38: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, VREF = 0.5 x VDD = 2.75V. FIGURE 2-39: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, VREF = 0.5 x VDD = 1.35V. 2.2.7 Total Unadjusted Error (TUE) – MCP47CXB2X (12-Bit), VREF = Internal Band Gap (VRXB:VRXA = 01), Code 64-4032 FIGURE 2-40: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 1x. FIGURE 2-41: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 2x. FIGURE 2-42: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 1x. FIGURE 2-43: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 1x. FIGURE 2-44: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 2x. FIGURE 2-45: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 1x. FIGURE 2-46: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 2x. FIGURE 2-47: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V, Gain = 1x. FIGURE 2-48: Total Unadjusted Error (VOUT) vs. DAC Code, 25°C, Gain = 1x. FIGURE 2-49: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 2x. FIGURE 2-50: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V, Gain = 1x. FIGURE 2-51: Total Unadjusted Error (VOUT) vs. DAC Code, 25°C, Gain = 2x. FIGURE 2-52: Total Unadjusted Error (VOUT) vs. DAC Code, +25°C, Gain = 1x and 2x. 2.2.8 Integral Nonlinearity Error (INL) – MCP47CXB2X (12-Bit), VREF = Internal Band Gap (VRXB:VRXA = 01), CODE 64-4032 FIGURE 2-53: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 1x. FIGURE 2-54: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 2x. FIGURE 2-55: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 1x. FIGURE 2-56: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 1x. FIGURE 2-57: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 2x. FIGURE 2-58: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 1x. FIGURE 2-59: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 2x. FIGURE 2-60: INL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V, Gain = 1x. FIGURE 2-61: INL Error vs. DAC Code, +25°C, Gain = 1x. FIGURE 2-62: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 2x. FIGURE 2-63: INL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V, Gain = 1x. FIGURE 2-64: INL Error vs. DAC Code, +25°C, Gain = 2x. FIGURE 2-65: INL Error vs. DAC Code, +25°C, Gain = 1x and 2x. 2.2.9 Differential Nonlinearity Error (DNL) – MCP47CXB2X (12-Bit), VREF = Internal Band Gap (VRXB:VRXA = 01), Code 64-4032 FIGURE 2-66: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 1x. FIGURE 2-67: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 5.5V, Gain = 2x. FIGURE 2-68: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 1x. FIGURE 2-69: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 1x. FIGURE 2-70: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 5.5V, Gain = 2x. FIGURE 2-71: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 1x. FIGURE 2-72: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 2.7V, Gain = 2x. FIGURE 2-73: DNL Error vs. DAC Code and Temperature (Single Channel – MCP47CXB21), VDD = 1.8V, Gain = 1x. FIGURE 2-74: DNL Error vs. DAC Code, +25°C, Gain = 1x. FIGURE 2-75: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 2.7V, Gain = 2x. FIGURE 2-76: DNL Error vs. DAC Code and Temperature (Dual Channel – MCP47CXB22), VDD = 1.8V, Gain = 1x. FIGURE 2-77: DNL Error vs. DAC Code, +25°C, Gain = 2x. FIGURE 2-78: DNL Error vs. DAC Code, +25°C, Gain = 1x and 2x. 3.0 Pin Descriptions TABLE 3-1: MCP47CXBX1 (Single DAC) Pin Function Table TABLE 3-2: MCP47CXBX2 (Dual DAC) Pin Function Table 3.1 Positive Power Supply Input (VDD) 3.2 Ground (VSS) 3.3 Voltage Reference Pin (VREF) 3.4 Analog Output Voltage Pins (VOUT0, VOUT1) 3.5 Latch/High-Voltage Command Pin (LAT/HVC) 3.6 I2C – Serial Clock Pin (SCL) 3.7 I2C – Serial Data Pin (SDA) 3.8 I2C Slave Address Pins (A0,A1) 3.9 No Connect (NC) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) 4.1.1 Power-on Reset FIGURE 4-1: Power-on Reset Operation. 4.1.2 Brown-out Reset 4.2 Device Memory 4.2.1 Volatile Register Memory (RAM) TABLE 4-1: MCP47CXBXX Memory Map (16-Bit) 4.2.2 Nonvolatile Register Memory (MTP) 4.2.3 POR/BOR Operation with WiperLock Technology Enabled 4.2.4 Unimplemented Locations TABLE 4-2: Factory Default POR/BOR Values (MTP Memory Unprogrammed) 4.2.5 Device Registers Register 4-1: DAC0 (00h/10h) and DAC1 (01h/11h) Output Value Registers (Volatile/Nonvolatile) Register 4-2: Voltage Reference (VREF) Control Registers (08h/18h) (Volatile/Nonvolatile) Register 4-3: Power-Down Control Registers (09h/19h) (Volatile/Nonvolatile) Register 4-4: Gain Control and System Status Register (0Ah) (Volatile) Register 4-5: Gain Control and Slave Address Register (1AH) (Nonvolatile) Register 4-6: WiperLock™ Technology Control Register (1Bh) (Nonvolatile) 5.0 DAC Circuitry FIGURE 5-1: MCP47CXBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. EQUATION 5-1: RS Calculation 5.2 Voltage Reference Selection FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.2.1 Using VDD as VREF 5.2.2 Using an External VREF Source in Unbuffered Mode 5.2.3 Using an External VREF Source in Buffered Mode 5.2.4 Using the Internal Band Gap as Voltage Reference TABLE 5-1: VOUT Using Band Gap 5.3 Output Buffer/VOUT Operation FIGURE 5-5: Output Driver Block Diagram. 5.3.1 Programmable Gain TABLE 5-2: Output Driver Gain 5.3.2 Output Voltage EQUATION 5-2: Calculating Output Voltage (VOUT) 5.3.3 Step Voltage (VS) EQUATION 5-3: VS Calculation TABLE 5-3: Theoretical Step Voltage (VS)(1) 5.3.4 Output Slew Rate FIGURE 5-6: VOUT Pin Slew Rate. 5.3.5 Driving Resistive and Capacitive Loads FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). 5.4 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example Use of LAT Pin Operation. 5.5 Power-Down Operation TABLE 5-4: Power-Down Bits and Output Resistive Load TABLE 5-5: DAC Current Sources 5.5.1 Exiting Power-Down TABLE 5-6: DAC Input Code vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 6.0 I2C Serial Interface Module FIGURE 6-1: Typical I2C Interface. 6.1 Overview 6.1.1 Interface Pins (SCL and SDA) 6.2 Communication Data Rates 6.3 POR/BOR 6.4 Device Memory Address 6.5 General Call Commands 6.6 Multi-Master Systems 6.7 Device I2C Slave Addressing FIGURE 6-2: Slave Address Bits in the I2C Control Byte. TABLE 6-1: I2C Address/Order Code 6.7.1 Custom I2C Slave Address Options 6.8 Slope Control 6.9 Pulse Gobbler 6.10 Entering High-Speed (HS) Mode FIGURE 6-3: HS Mode Sequence. 7.0 Device Commands 7.1 Write Commands 7.2 Read Commands TABLE 7-1: Device Commands – Number of Clocks 7.3 General Call Commands 7.4 Aborting a Transmission 7.5 Write Command 7.5.1 Single Write to Volatile Memory 7.5.2 Single Write to Nonvolatile Memory (HVC Pin = VIL or VIH) 7.5.3 Single Write to Nonvolatile Memory (HVC Pin = VIHH) FIGURE 7-1: Write Random Address Command. 7.5.4 Continuous Writes to Volatile Memory TABLE 7-2: Volatile Memory Addresses 7.5.5 Continuous Writes to Nonvolatile Memory FIGURE 7-2: I2C ACK/NACK Behavior (Write Command Example). FIGURE 7-3: Continuous Write Commands (Volatile Memory Only). 7.6 Read Command 7.6.1 Single Read 7.6.2 Continuous Reads 7.6.3 Ignoring an I2C Transmission and “Falling Off” the Bus FIGURE 7-4: Read Command – Single Memory Address. FIGURE 7-5: Read Command – Last Memory Address Accessed. FIGURE 7-6: I2C ACK/NACK Behavior (Read Command Example). FIGURE 7-7: Continuous Read Command of Specified Address. 7.7 General Call Commands FIGURE 7-8: General Call Formats. 7.7.1 General Call Reset 7.7.2 General Call Wake-up FIGURE 7-9: General Call Reset Command. FIGURE 7-10: General Call Wake-up Command. 8.0 Typical Applications 8.1 Connecting to the I2C Bus Using Pull-up Resistors 8.1.1 Device Connection Test FIGURE 8-1: I2C Bus Connection Test. 8.2 Power Supply Considerations FIGURE 8-2: Example Circuit. 8.3 Application Examples 8.3.1 DC Set Point or Calibration FIGURE 8-3: Example Circuit of Set Point or Threshold Calibration. EQUATION 8-1: VOUT and VTRIP Calculations FIGURE 8-4: Single-Supply “Window” DAC. EQUATION 8-2: VOUT and VTRIP Calculations 8.4 Bipolar Operation FIGURE 8-5: Digitally Controlled Bipolar Voltage Source Example Circuit. EQUATION 8-3: VOUT, VOA+ and VO Calculations 8.5 Selectable Gain and Offset Bipolar Voltage Output 8.5.1 Bipolar DAC Example EQUATION 8-4: EQUATION 8-5: FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. EQUATION 8-6: VOUT, VOA+ and VO Calculations EQUATION 8-7: Bipolar “Window” DAC Using R4 and R5 8.6 Designing a Double Precision DAC FIGURE 8-7: Simple Double Precision DAC Using MCP47CVBX2. EQUATION 8-8: VOUT Calculation 8.7 Building Programmable Current Source FIGURE 8-8: Digitally-Controlled Current Source. 8.8 Serial Interface Communication Times 8.9 Software I2C Interface Reset Sequence FIGURE 8-9: Software Reset Sequence Format. 8.10 Design Considerations 8.10.1 Power Supply Considerations FIGURE 8-10: Typical Microcontroller Connections. 8.10.2 Layout Considerations TABLE 8-1: Package Footprint(1) 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Development Tools(1) TABLE 9-2: Technical Documentation FIGURE 9-1: MCP47CXBXX Evaluation Board Circuit Using ADM00309. 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Revision B (June 2019) Revision A (September 2018) Appendix B: I2C Serial Interface FIGURE B-1: Typical I2C Interface. B.1 Overview B.2 Signal Descriptions B.2.1 Serial Data (SDA) B.2.2 Serial Clock (SCL) B.3 I2C Operation B.3.1 I2C Bit States and Sequence FIGURE B-2: Start Bit. FIGURE B-3: Data Bit. FIGURE B-4: Acknowledge Waveform. TABLE B-1: MCP47CXBXX A/A Responses FIGURE B-5: Repeated Start Condition Waveform. FIGURE B-6: Stop Condition Receive or Transmit Mode. B.3.2 Clock Stretching B.3.3 Aborting a Transmission FIGURE B-7: Typical 8-Bit I2C Waveform Format. FIGURE B-8: I2C Data States and Bit Sequence. B.3.4 Slope Control B.3.5 Device Addressing FIGURE B-9: I2C Slave Address Control Byte. B.3.6 HS Mode FIGURE B-10: HS Mode Sequence. B.3.7 General Call FIGURE B-11: General Call Formats. Appendix C: Terminology C.1 Resolution C.2 Least Significant Bit (LSb) EQUATION C-1: LSb Voltage Calculation C.3 Monotonic Operation FIGURE C-1: VW (VOUT). C.4 Full-Scale Error (EFS) EQUATION C-2: Full-Scale Error C.5 Zero-Scale Error (EZS) EQUATION C-3: Zero-Scale Error C.6 Total Unadjusted Error (ET) EQUATION C-4: Total Unadjusted Error Calculation C.7 Offset Error (EOS) FIGURE C-2: Offset Error (Zero Gain Error). C.8 Offset Error Drift (EOSD) C.9 Gain Error (EG) FIGURE C-3: Gain Error and Full-Scale Error Example. EQUATION C-5: Gain Error Example C.10 Gain Error Drift (EGD) C.11 Integral Nonlinearity (INL) EQUATION C-6: INL Error FIGURE C-4: INL Accuracy. C.12 Differential Nonlinearity (DNL) EQUATION C-7: DNL Error FIGURE C-5: DNL Accuracy. C.13 Settling Time C.14 Major Code Transition Glitch C.15 Digital Feedthrough C.16 -3 dB Bandwidth C.17 Power Supply Sensitivity (PSS) EQUATION C-8: PSS Calculation C.18 Power Supply Rejection Ratio (PSRR) C.19 VOUT Temperature Coefficient C.20 Absolute Temperature Coefficient C.21 Noise Spectral Density Product Identification System Worldwide Sales and Service