AD1835APIN CONFIGURATIONDGNDCCLKCOUTASDATAODVDDMCLKALRCLKABCLKDSDATA4DSDATA3DSDATA2DSDATA1DGND52515049484746454443424140DVDD139 DVDDCLATCH238 DBCLKCIN337 DLRCLKPD/RST436 M/SAGND535 AGNDOUTLN1634 OUTRP4AD1835ATOP VIEWOUTLP1733 OUTRN4(Not to Scale)OUTRN1832 OUTLP4OUTRP1931 OUTLN4AGND 1030 AGNDAVDD 1129 AVDDOUTLN2 1228 OUTRP3OUTLP2 1327 OUTRN314151617181920212223242526AGNDFILTDFILTRAVDDAGNDADCLNADCLPADCRNADCRPOUTRN2OUTRP2OUTLN3OUTLP3PIN FUNCTION DESCRIPTIONSInput/Pin NumberMnemonicOutputDescription 1, 39 DVDD Digital Power Supply. Connect to digital 5 V supply. 2 CLATCH I Latch Input for Control Data. 3 CIN I Serial Control Input. 4 PD/RST I Power-Down/Reset. 5, 10, 16, 24, 30, 35 AGND Analog Ground. 6, 12, 25, 31 OUTLNx O DACx Left Channel Negative Output. 7, 13, 26, 32 OUTLPx O DACx Left Channel Positive Output. 8, 14, 27, 33 OUTRNx O DACx Right Channel Negative Output. 9, 15, 28, 34 OUTRPx O DACx Right Channel Positive Output. 11, 19, 29 AVDD Analog Power Supply. Connect to analog 5 V supply. 17 FILTD Filter Capacitor Connection. Recommended 10 µF/100 nF. 18 FILTR Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. 20 ADCLN I ADC Left Channel Negative Input. 21 ADCLP I ADC Left Channel Positive Input. 22 ADCRN I ADC Right Channel Negative Input. 23 ADCRP I ADC Right Channel Positive Input. 36 M/S I ADC Master/Slave Select. 37 DLRCLK I/O DAC LR Clock. 38 DBCLK I/O DAC Bit Clock. 40, 52 DGND Digital Ground. 41 to 44 DSDATAx I DACx Input Data (Left and Right Channels). 45 ABCLK I/O ADC Bit Clock. 46 ALRCLK I/O ADC LR Clock. 47 MCLK I Master Clock Input. 48 ODVDD Digital Output Driver Power Supply. 49 ASDATA O ADC Serial Data Output. 50 COUT O Output for Control Data. 51 CCLK I Control Clock Input for Control Data. REV. A –7– Document Outline FEATURES APPLICATIONS PRODUCT OVERVIEW FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DEFINITIONS Dynamic Range Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)] Pass Band Pass-Band Ripple Stop Band Gain Error Interchannel Gain Mismatch Gain Drift Crosstalk (EIAJ Method) Power Supply Rejection Group Delay Group Delay Variation GLOSSARY FUNCTIONAL OVERVIEW ADCs DACs DAC and ADC Coding AD1835A CLOCKING SCHEME Selecting DAC Sampling Rate Selecting an ADC Sample Rate RESET and Power-Down Power Supply and Voltage Reference Serial Control Port Serial Data Ports—Data Format Packed Modes Auxiliary (TDM) Mode CONTROL/STATUS REGISTERS DAC Control Registers Sample Rate Power-Down/Reset DAC Data-Word Width DAC Data Format De-emphasis Mute DAC Stereo Replicate DAC Volume Control ADC Control Registers ADC Peak Level Sample Rate ADC Power-Down High-Pass Filter ADC Data-Word Width ADC Data Format Master/Slave Auxiliary Mode ADC Peak Readback CASCADE MODE Dual AD1835A Cascade OUTLINE DIMENSIONS Revision History