Datasheet AD1835A (Analog Devices) - 5

AD1835A Parameter Min Max Unit Comments
TDM256 MODE (Master, 48 kHz and 96 kHz) tTBD BCLK Delay 40 ns From MCLK Rising tFSD FSTDM Delay 5 ns From BCLK Rising tTABDD ASDATA Delay 10 ns From BCLK Rising tTDDS DSDATA1 Setup 15 ns To BCLK Falling tTDDH DSDATA1 Hold 15 ns From BCLK Falling TDM256 MODE (Slave, 48 kHz and 96 kHz) fAB BCLK Frequency 256 ⫻ fS tTBCH BCLK High 17 ns tTBCL BCLK Low 17 ns tTFS FSTDM Setup 10 ns To BCLK Falling tTFH FSTDM Hold 10 ns From BCLK Falling tTBDD ASDATA Delay 15 ns From BCLK Rising tTDDS DSDATA1 Setup 15 ns To BCLK Falling tTDDH DSDATA1 Hold 15 ns From BCLK Falling TDM512 MODE (Master, 48 kHz) tTBD BCLK Delay 40 ns From MCLK Rising tFSD FSTDM Delay 5 ns From BCLK Rising tTABDD ASDATA Delay 10 ns From BCLK Rising tTDDS DSDATA1 Setup 15 ns To BCLK Falling tTDDH DSDATA1 Hold 15 ns From BCLK Falling TDM512 MODE (Slave, 48 kHz ) fAB BCLK Frequency 512 ⫻ fS tTBCH BCLK High 17 ns tTBCL BCLK Low 17 ns tTFS FSTDM Setup 10 ns To BCLK Falling tTFH FSTDM Hold 10 ns From BCLK Falling tTBDD ASDATA Delay 15 ns From BCLK Rising tTDDS DSDATA1 Setup 15 ns To BCLK Falling tTDDH DSDATA1 Hold 15 ns From BCLK Falling AUXILIARY INTERFACE (48 kHz and 96 kHz) tAXDS AAUXDATA Setup 10 ns To AUXBCLK Rising tAXDH AAUXDATA Hold 10 ns From AUXBCLK Rising fABP AUXBCLK Frequency 64 ⫻ fS Slave Mode tAXBH AUXBCLK High 15 ns tAXBL AUXBCLK Low 15 ns tAXLS AUXLRCLK Setup 10 ns To AUXBCLK Rising tAXLH AUXLRCLK Hold 10 ns From AUXBCLK Rising Master Mode tAUXLRCLK AUXLRCLK Delay 15 ns From AUXBCLK Falling tAUXBCLK AUXBCLK Delay 20 ns From MCLK Rising Specifications subject to change without notice.
tMCLK tMH MCLK tML PD/RST tPDR
Figure 1. MCLK and PD/ RST Timing REV. A –5– Document Outline FEATURES APPLICATIONS PRODUCT OVERVIEW FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DEFINITIONS Dynamic Range Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)] Pass Band Pass-Band Ripple Stop Band Gain Error Interchannel Gain Mismatch Gain Drift Crosstalk (EIAJ Method) Power Supply Rejection Group Delay Group Delay Variation GLOSSARY FUNCTIONAL OVERVIEW ADCs DACs DAC and ADC Coding AD1835A CLOCKING SCHEME Selecting DAC Sampling Rate Selecting an ADC Sample Rate RESET and Power-Down Power Supply and Voltage Reference Serial Control Port Serial Data Ports—Data Format Packed Modes Auxiliary (TDM) Mode CONTROL/STATUS REGISTERS DAC Control Registers Sample Rate Power-Down/Reset DAC Data-Word Width DAC Data Format De-emphasis Mute DAC Stereo Replicate DAC Volume Control ADC Control Registers ADC Peak Level Sample Rate ADC Power-Down High-Pass Filter ADC Data-Word Width ADC Data Format Master/Slave Auxiliary Mode ADC Peak Readback CASCADE MODE Dual AD1835A Cascade OUTLINE DIMENSIONS Revision History