Datasheet ADSP-21065L (Analog Devices) - 8

ADSP-21065L Pin Type Function
HBR I/A
Host Bus Request.
Must be asserted by a host processor to request control of the ADSP- 21065L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP- 21065L places the address, data, select, and strobe lines in a high impedance state. It does, however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L bus requests (BR2-1) in a multiprocessor system. HBG I/O
Host Bus Grant
. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released. In a multiprocessor system, HBG is output by the ADSP-21065L bus master. CS I/A
Chip Select.
Asserted by host processor to select the ADSP-21065L. REDY (O/D) O
Host Bus Acknowledge.
The ADSP-21065L deasserts REDY to add wait states to an asyn- chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted. DMAR1 I/A
DMA Request 1
(DMA Channel 9). DMAR2 I/A
DMA Request 2
(DMA Channel 8). DMAG1 O/T
DMA Grant 1
(DMA Channel 9). DMAG2 O/T
DMA Grant 2
(DMA Channel 8). BR2-1 I/O/S
Multiprocessing Bus Requests.
Used by multiprocessing ADSP-21065Ls to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID2-0 inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD. ID1-0 I
Multiprocessing ID.
Determines which multiprocessor bus request (BR1–BR2) is used by ADSP-21065L. ID = 01 corresponds to BR1, ID = 10 corresponds to BR2. ID = 00 in single- processor systems. These lines are a system configuration selection which should be hard-wired or changed only at reset. CPA (O/D) I/O
Core Priority Access.
Asserting its CPA pin allows the core processor of an ADSP-21065L bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an internal 5 kW pull-up resistor. If core access priority is not required in a system, leave the CPA pin unconnected. DTxX O
Data Transmit
(Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kW internal pull- up resistor. DRxX I
Data Receive
(Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kW internal pull-up resistor. TCLKx I/O
Transmit Clock
(Serial Ports 0, 1). Each TCLK pin has a 50 kW internal pull-up resistor. RCLKx I/O
Receive Clock
(Serial Ports 0, 1). Each RCLK pin has a 50 kW internal pull-up resistor. TFSx I/O
Transmit Frame Sync
(Serial Ports 0, 1). RFSx I/O
Receive Frame Sync
(Serial Ports 0, 1). BSEL I
EPROM Boot Select.
When BSEL is high, the ADSP-21065L is configured for booting from an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See BMS for details. This signal is a system configuration selection which should be hardwired. –8– REV. C Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History