Datasheet ADSP-21065L (Analog Devices) - 4

ADSP-21065L
structures required in digital signal processing, and are com-
Off-Chip Memory and Peripherals Interface
monly used in digital filters and Fourier transforms. The The ADSP-21065L’s external port provides the processor’s ADSP-21065L’s two DAGs contain sufficient registers to allow interface to off-chip memory and peripherals. The 64M words, the creation of up to 32 circular buffers (16 primary register off-chip address space is included in the ADSP-21065L’s sets, 16 secondary). The DAGs automatically handle address unified address space. The separate on-chip buses—for program pointer wraparound, reducing overhead, increasing perfor- memory, data memory and I/O—are multiplexed at the external mance, and simplifying implementation. Circular buffers can port to create an external system bus with a single 24-bit start and end at any memory location. address bus, four memory selects, and a single 32-bit data bus. The on-chip Super Harvard Architecture provides three bus
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel performance, while the off-chip unified address space gives operations, for concise programming. For example, the ADSP- flexibility to the designer. 21065L can conditionally execute a multiply, an add, a subtract
SDRAM Interface
and a branch, all in a single instruction. The SDRAM interface enables the ADSP-21065L to transfer data to and from synchronous DRAM (SDRAM) at 2x clock
ADSP-21065L FEATURES
frequency. The synchronous approach coupled with 2x clock The ADSP-21065L is designed to achieve the highest system frequency supports data transfer at a high throughput—up to throughput to enable maximum system performance. It can be 220 Mbytes/sec. clocked by either a crystal or a TTL-compatible clock signal. The SDRAM interface provides a glueless interface with stan- The ADSP-21065L uses an input clock with a frequency equal dard SDRAMs—16 Mb, 64 Mb, and 128 Mb—and includes to half the instruction rate—a 33 MHz input clock yields a options to support additional buffers between the ADSP-21065L 15 ns processor cycle (which is equivalent to 66 MHz). Inter- and SDRAM. The SDRAM interface is extremely flexible and faces on the ADSP-21065L operate as shown below. Hereafter provides capability for connecting SDRAMs to any one of the in this document, 1x = input clock frequency, and 2x = processor’s ADSP-21065L’s four external memory banks. instruction rate. Systems with several SDRAM devices connected in parallel may The following clock operation ratings are based on 1x = 33 MHz require buffering to meet overall system timing requirements. (instruction rate/core = 66 MHz): The ADSP-21065L supports pipelining of the address and SDRAM 66 MHz control signals to enable such buffering between itself and External SRAM 33 MHz multiple SDRAM devices. Serial Ports 33 MHz
Host Processor Interface
Multiprocessing 33 MHz The ADSP-21065L’s host interface provides easy connection to Host (Asynchronous) 33 MHz standard microprocessor buses—8-, 16-, and 32-bit—requiring Augmenting the ADSP-21000 family core, the ADSP-21065L little additional hardware. Supporting asynchronous transfers at adds the following architectural features: speeds up to 1x clock frequency, the host interface is accessed through the ADSP-21065L’s external port. Two channels of
Dual-Ported On-Chip Memory
The ADSP-21065L contains 544 Kbits of on-chip SRAM, DMA are available for the host interface; code and data trans- organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has fers are accomplished with low software overhead. 256 Kbits. Bank 0 is configured with 9 columns of 2K ¥ 16 bits, The host processor requests the ADSP-21065L’s external bus and Bank 1 is configured with 8 columns of 2K ¥ 16 bits. Each with the host bus request (HBR), host bus grant (HBG), and memory block is dual-ported for single-cycle, independent accesses ready (REDY) signals. The host can directly read and write the by the core processor and I/O processor or DMA controller. IOP registers of the ADSP-21065L and can access the DMA The dual-ported memory and separate on-chip buses allow two channel setup and mailbox registers. Vector interrupt support data transfers from the core and one from I/O, all in a single enables efficient execution of host commands. cycle (see Figure 4 for the ADSP-21065L Memory Map).
DMA Controller
On the ADSP-21065L, the memory can be configured as a The ADSP-21065L’s on-chip DMA controller allows zero- maximum of 16K words of 32-bit data, 34K words for 16-bit overhead, nonintrusive data transfers without processor inter- data, 10K words of 48-bit instructions (and 40-bit data) or vention. The DMA controller operates independently and combinations of different word sizes up to 544 Kbits. All the invisibly to the processor core, allowing DMA operations to memory can be accessed as 16-bit, 32-bit or 48-bit. occur while the core is simultaneously executing its program While each memory block can store combinations of code and instructions. data, accesses are most efficient when one block stores data, DMA transfers can occur between the ADSP-21065L’s internal using the DM bus for transfers, and the other block stores memory and either external memory, external peripherals, or a instructions and data, using the PM bus for transfers. Using the host processor. DMA transfers can also occur between the DM and PM busses in this way, with one dedicated to each ADSP-21065L’s internal memory and its serial ports. DMA memory block, assures single-cycle execution with two data transfers between external memory and external peripheral transfers. In this case, the instruction must be available in the devices are another option. External bus packing to 16-, 32-, or cache. Single-cycle execution is also maintained when one of 48-bit internal words is performed during DMA transfers. the data operands is transferred to or from off-chip, via the Ten channels of DMA are available on the ADSP-21065L— ADSP-21065L’s external port. eight via the serial ports, and two via the processor’s external port (for either host processor, other ADSP-21065L, memory or –4– REV. C Document Outline SUMMARY KEY FEATURES Flexible Data Formats and 40-Bit Extended Precision Parallel Computations 544 Kbits Configurable On-Chip SRAM DMA Controller Host Processor Interface Multiprocessing Serial Ports GENERAL DESCRIPTION ADSP-21000 FAMILY CORE ARCHITECTURE Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Two Operands Instruction Cache Data Address Generators with Hardware Circular Buffers Flexible Instruction Set ADSP-21065L FEATURES Dual-Ported On-Chip Memory Off-Chip Memory and Peripherals Interface SDRAM Interface Host Processor Interface DMA Controller Serial Ports Programmable Timers and General-Purpose I/O Ports Program Booting Multiprocessing DEVELOPMENT TOOLS Additional Information PIN DESCRIPTIONS CLOCK SIGNALS TARGET BOARD CONNECTOR FOR EZ-ICE PROBE SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION ADSP-21065L TIMING SPECIFICATIONS General Notes Memory Read—Bus Master Memory Write—Bus Master Synchronous Read/Write—Bus Master Synchronous Read/Write—Bus Slave Multiprocessor Bus Request and Host Bus Request Asynchronous Read/Write—Host to ADSP-21065L Three-State Timing—Bus Master, Bus Slave, HBR, SBTS DMA Handshake SDRAM Interface—Bus Master SDRAM Interface—Bus Slave Serial Ports JTAG Test Access Port and Emulation OUTPUT DRIVE CURRENT TEST CONDITIONS Output Disable Time Example System Hold Time Calculation Capacitive Loading POWER DISSIPATION ENVIRONMENTAL CONDITIONS Thermal Characteristics 208-LEAD MQFP PIN CONFIGURATION 208-LEAD MQFP PIN OUTLINE DIMENSIONS 208-Lead Plastic Quad Flatpack Package [MQFP] 196-BALL MINI-BGA PIN CONFIGURATION 196-BALL MINI-BGA PIN CONFIGURATION ORDERING GUIDE OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Revision History