Datasheet ADSP-21369 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | SHARC Processor |
| Páginas / Página | 60 / 2 — ADSP-21369. TABLE OF CONTENTS. REVISION HISTORY. 3/2019—Rev. G to Rev. H |
| Revisión | H |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
ADSP-21369. TABLE OF CONTENTS. REVISION HISTORY. 3/2019—Rev. G to Rev. H
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ADSP-21369 TABLE OF CONTENTS
General Description ... 3 Maximum Power Dissipation ... 17 SHARC Family Core Architecture .. 4 Absolute Maximum Ratings ... 18 Family Peripheral Architecture .. 7 Timing Specifications ... 18 I/O Processor Features ... 10 Output Drive Currents ... 50 System Design .. 10 Test Conditions .. 50 Development Tools ... 11 Capacitive Loading .. 50 Additional Information .. 12 Thermal Characteristics .. 52 Related Signal Chains .. 12 256-Ball BGA_ED Pinout ... 53 Pin Function Descriptions ... 13 208-Lead LQFP_EP Pinout ... 56 Specifications .. 16 Package Dimensions ... 58 Operating Conditions .. 16 Surface-Mount Design .. 59 Electrical Characteristics ... 17 Ordering Guide ... 60 ESD Caution .. 17
REVISION HISTORY 3/2019—Rev. G to Rev. H
Deleted obsolete models ADSP-21367 and ADSP-21368 throughout data sheet. Reorganized layout of data sheet. Rev. H | Page 2 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide
ADSP-21369 TABLE OF CONTENTS
General Description ... 3 Maximum Power Dissipation ... 17 SHARC Family Core Architecture .. 4 Absolute Maximum Ratings ... 18 Family Peripheral Architecture .. 7 Timing Specifications ... 18 I/O Processor Features ... 10 Output Drive Currents ... 50 System Design .. 10 Test Conditions .. 50 Development Tools ... 11 Capacitive Loading .. 50 Additional Information .. 12 Thermal Characteristics .. 52 Related Signal Chains .. 12 256-Ball BGA_ED Pinout ... 53 Pin Function Descriptions ... 13 208-Lead LQFP_EP Pinout ... 56 Specifications .. 16 Package Dimensions ... 58 Operating Conditions .. 16 Surface-Mount Design .. 59 Electrical Characteristics ... 17 Ordering Guide ... 60 ESD Caution .. 17
REVISION HISTORY 3/2019—Rev. G to Rev. H
Deleted obsolete models ADSP-21367 and ADSP-21368 throughout data sheet. Reorganized layout of data sheet. Rev. H | Page 2 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide