Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 8

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ADSP-21562/21563/21565 Preliminary Technical Data Additional Features
• Storage for additional data for the SHARC+ core to avoid external memory latencies and reduce external memory To enhance the reliability of the application, L1 data RAMs sup- bandwidth port parity error detection logic for every byte. Additionally, the processors detect illegal opcodes. Core interrupts flag both • Storage for data coefficient tables cached by the errors. Master ports of the core also detect for failed external SHARC+ core accesses. See System Memory Protection Unit (SMPU) section for
SYSTEM INFRASTRUCTURE
options in limiting access by the core and DMA masters. The following sections describe the system infrastructure of the
One Time Programmable Memory (OTP)
ADSP-2156x processors. The processors feature 7 Kb of one time programmable (OTP) memory which is memory-map accessible. This memory can be
System L2 Memory
programmed with custom keys and it supports secure boot and A system L2 SRAM memory of up to 8 Mb (1 MB) is available to secure operation. the SHARC+ core and the system DMA channels (see Table 3). The L2 SRAM block is subdivided into eight banks to support
I/O Memory Space
concurrent access to the L2 memory ports. Memory accesses to Mapped I/Os include SPI2 or OSPI0 memory address spaces the L2 memory space are multicycle accesses by the SHARC+ (see Table 5). core. The memory space is used for various situations including • Accelerator and peripheral sources and destination mem- ory to avoid accessing data in the external memory • A location for DMA descriptors
SYSTEM MEMORY MAP Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+® Addressing Memory Map (Private Address Space) Extended Precision/ Short Word/ Memory Long Word (64 Bits) ISA Code (48 Bits) Normal Word (32 Bits) VISA Code (16 Bits) Byte Access (8 Bits)
L1 Block 0 SRAM 0x00048000– 0x00090000– 0x00090000– 0x00120000– 0x00240000– (1.5 Mb) 0x0004DFFF 0x00097FFF 0x0009BFFF 0x00137FFF 0x0026FFFF L1 Block 1 SRAM 0x00058000– 0x000B0000– 0x000B0000– 0x00160000– 0x002C0000– (1.5 Mb) 0x0005DFFF 0x000B7FFF 0x000BBFFF 0x00177FFF 0x002EFFFF L1 Block 2 SRAM 0x00060000– 0x000C0000– 0x000C0000– 0x00180000– 0x00300000– (1 Mb) 0x00063FFF 0x000C5554 0x000C7FFF 0x0018FFFF 0x0031FFFF L1 Block 3 SRAM 0x00070000– 0x000E0000– 0x000E0000– 0x001C0000– 0x00380000– (1 Mb) 0x00073FFF 0x000E5554 0x000E7FFF 0x001CFFFF 0x0039FFFF
Table 3. L2 Memory Addressing Map Byte Address Space Normal Word Address Space VISA Address Space ISA Address Space Memory1 SHARC+ Data Access SHARC+ Data Address SHARC+ Instruction Fetch SHARC+ Instruction Fetch
L2 RAM (2 Mb) 0x200C0000–0x200FFFFF 0x08030000–0x0803FFFF 0x00BE0000–0x00BFFFFF 0x005E0000–0x005EAAAA L2 RAM (4 Mb) 0x20080000–0x200FFFFF 0x08020000–0x0803FFFF 0x00BC0000–0x00BFFFFF 0x005D5556–0x005EAAAA L2 RAM (8 Mb) 0x20000000–0x200FFFFF 0x08000000–0x0803FFFF 0x00B80000–0x00BFFFFF 0x005C0000–0x005EAAAA L2 Boot ROM0 SHARC/DMA: 0x20100000–0x20107FFF 0x08040000–0x08041FFF 0x00B20000–0x00B23FFF 0x00580000–0x00581555 L2 Boot ROM1 0x20108000–0x2010FFFF 0x08042000–0x08043FFF 0x00B00000–0x00B03FFF 0x00500000–0x00501555 L2 Boot ROM2 0x20110000–0x20117FFF 0x08044000–0x08045FFF 0x00B40000–0x00B43FFF 0x00540000–0x00541555 1 The L2 RAM blocks are subdivided into banks—the 8 Mb L2 models have eight banks, the 4 Mb models have four banks, and there are two banks for the 2 Mb models. Rev. PrG | Page 8 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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