Datasheet LYTSwitch-6 (Power Integrations) - 10

LYTSwitch-6
provides current path for the charging of the bulk capacitor C4 − 2. Efficiency assumptions depend on power level. Smal est device especial y at low-line, which improves efficiency. Free-wheel diodes power levels assume efficiency >84% increasing to >89% for the D1 and D17 provide a current path for the energy stored in the PFC largest device. inductor that must be transferred to the secondary-side during switch 3. Transformer primary inductance tolerance is ±10%. off-time. The series connection of D1 and D17 are able to withstand 4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at the resonant voltage ring from the PFC inductor when the switch minimum input voltage for universal line, and KP = 1 for high turns off. input line (only) designs. During a no-load or light load condition (<10% load) the energy 5. Maximum conduction loss for adapters is limited to 0.6 W and to stored in the PFC inductor is greater than required by the secondary 0.8 W for open frame designs. load. The excess energy from the PFC inductor is therefore recycled 6. Increased current limit is selected for peak and open-frame to the bulk capacitor C4 boosting the voltage level. A Zener-resistor power columns, while standard current limit is used for adapter clamp comprising of VR1 and VR2 in series with R47 is connected columns. across the bulk capacitor C4 to clamp this voltage below the 7. The part is board-mounted with SOURCE pins soldered to a voltage-rating of C4. This Zener clamp voltage should be ≤450 V sufficient area of copper and/or a heat sink to keep the SOURCE (the maximum voltage rating of bulk capacitor C4). In the event of pin temperature ≤110 °C. an input line surge or transient event, the primary switch is protected 8. Ambient temperature limit is 50 °C for open frame designs and from overvoltage by the INPUT VOLTAGE pin sense resistors which 40 °C for sealed adapters. trigger a line overvoltage shutdown at 460 V. 9. Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power delivery, due to premature
Secondary Stage
termination of switching cycles, a transient KP limit of ≥0.6 is The secondary-side control of the LYTSwitch-6 IC provides constant specified. This prevents the initial current limit (I ) from being output voltage and constant output current. The voltage produced INT exceeded at switch turn-on. on the secondary winding of transformer T2 is rectified by D10 and 10. LYTSwitch-6 parts are unique in that the designer can set the filtered by the output capacitors C16 and C18. Adding an RC snubber switching frequency between 25 kHz to 95 kHz by adjusting (R48 and C14) across the output diode reduces voltage stress. In this transformer design. One way to lower device temperature is to design, the SYNCHRONOUS RECTIFIER DRIVE pin is connected to design the transformer to reduce switching frequency; a good the SECONDARY GROUND pin to al ow the use of a low-cost ultrafast starting point is 50 kHz. output diode instead of an SR FET.
Primary-Side Overvoltage Protection
The IC secondary is self-powered from either the secondary winding Primary-side output overvoltage protection provided by the forward voltage via the FORWARD pin, or the output voltage via the LYTSwitch-6 IC uses an internal protection that is triggered by a OUTPUT VOLTAGE pin. Decoupling capacitor C13 is connected to the threshold current of I into the PRIMARY BYPASS pin. For the SECONDARY BYPASS pin. In order to meet the maximum voltage SD bypass capacitor to be effective as a high frequency filter, the limits of OUTPUT VOLTAGE pin in this design, the secondary-side of capacitor should be located as close as possible to the SOURCE and the IC needs to be powered from a low voltage auxiliary supply PRIMARY BYPASS pins of the device. (winding FL3 and FL4). The FORWARD pin has to be connected to the same output to insure good regulation and high efficiency. This The primary sensed OVP function can be realized by connecting a auxiliary supply is rectified and filtered by D11 and C15 respectively. series combination of a Zener diode, a resistor and a blocking diode from the rectified and filtered bias-winding-voltage supply to the During constant voltage operation, output voltage regulation is PRIMARY BYPASS pin (see Figure 11-a). The rectified and filtered bias achieved by sensing the output voltage via a resistor network winding output voltage may be higher than anticipated (up to comprising R29 and R30. The voltage across R30 is monitored at 2 times the desired value) and is dependent on the coupling of the the FEEDBACK pin and compared to an internal reference voltage bias winding to the output winding and the resultant ringing of the threshold of 1.265 V. Bypass capacitor C19 is placed across the bias winding voltage waveform. It is recommended that the rectified FEEDBACK and SECONDARY GROUND pins to attenuate high bias winding voltage be measured. Ideal y this measurement should frequency noise that would otherwise couple to the feedback signal be made at the lowest input voltage and with maximum load applied and cause unwanted behavior such as pulse bunching. the output. This measured voltage should be used to select the During constant current operation, the maximum output current is set components required to achieve primary sensed OVP. It is by the sense resistors R43 and R24. The voltage across the sense recommended that a Zener diode is selected with a clamping voltage resistor is applied to the ISENSE pin internal reference threshold approximately 6 V lower than the rectified bias winding voltage at of 35 mV to maintain constant current regulation. Diode D13 in which OVP is expected to be triggered. A forward voltage drop of 1 V paral el with the current sense resistors clamps the voltage across the can be assumed for the blocking diode. A smal -signal standard ISENSE and SECONDARY GROUND pin. This shunts the high current recovery diode is recommended for this task. The blocking diode surge from the output capacitor seen during an output short-circuit prevents any reverse current from charging the bias capacitor during and prevents damage. start-up. Final y, the value of the series resistor required can be calculated such that a current higher than I will flow into the
Key Applications Design Considerations
SD PRIMARY BYPASS pin during an output overvoltage event.
Output Power Table Secondary-Side Overvoltage Protection
The output power table (Table 1) represents the maximum Secondary-side output overvoltage protection is provided by the continuous output power level that can be obtained under the LYTSwitch-6 IC which uses an internal auto-restart circuit triggered following conditions: by an input current into the SECONDARY BYPASS pin exceeding a 1. Minimum DC input voltage is ≥90 V for 85 VAC input and ≥220 V threshold of I . The direct sensed output OVP function can BPS(SD) for 230 VAC input (or 115 VAC with a voltage doubler). The be realized by connecting a Zener diode from the output to the voltage rating of the input capacitor should be set to meet these SECONDARY BYPASS pin. The Zener diode voltage needs to be the criteria.
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Rev. K 06/20 www.power.com Document Outline Product Highlights Description Output Power Table LYTSwitch-6 Functional Description Primary Controller Secondary Controller Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing MSL Table ESD and Latch-Up Table Part Ordering Information