Datasheet AOZ5312NQI (Alpha & Omega) - 6

AOZ5312NQI Electrical Characteristics(4)
TJ = 0°C to 150°C, VIN = 12V, VCC= PVCC = 5V, unless otherwise specified. Min/Max values are guaranteed by test, design, or statistical correlation.
Symbol Parameter Conditions Min. Typ. Max. Units GENERAL
VIN Power Stage Power Supply 2.5 20 V VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V R (5) Reference to High-Side MOSFET JC Thermal Resistance temperature rise 2.5 °C/W R (5) JA Freq = 300kHz. AOS Demo Board 12.5 °C/W
INPUT SUPPLY AND UVLO
VCC_UVLO VCC Rising 3.5 3.9 V Under-Voltage Lockout VCC_HYST VCC Hysteresis 400 mV DISB# = 0V 1 A SMOD# = 5V, PWM = 0V 550 A IVCC Control Circuit Bias Current SMOD# = 0V, PWM = 0V 535 A SMOD# = 0V, PWM =1.65V 430 A PWM = 400kHz, 20% Duty Cycle 17 mA IPVCC Drive Circuit Operating Current PWM = 1MHz, 20% Duty Cycle 42.5 mA
PWM INPUT
VPWMH Logic High Input Voltage 2.7 V VPWML Logic Low Input Voltage 0.72 V IPWM_SRC PWM = 0V -150 A PWM Pin Input Current IPWM_SNK PWM = 3.3V 150 A VTRI PWM Input Tri-State Window 1.35 1.95 V VPMW_FLOAT PWM Tri-State Voltage Clamp PWM = Floating 1.65 V
DISB# INPUT
VDISB#_ON Enable Input Voltage 2.0 V VDISB#_OFF Disable Input Voltage 0.8 V RDISB# DISB# Input Resistance Pull-Down Resistor 850 k
SMOD# INPUT
VSMOD#_H Logic High Input Voltage 2.0 V VSMOD#_L Logic Low Input Voltage 0.8 V RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 k
GATE DRIVER TIMING
tPDLU PWM to High-Side Gate PWM: H→L, VSWH: H→L 30 ns tPDLL PWM to Low-Side Gate PWM: L  H, GL: H  L 25 ns tPDHU Low-side to High-Side Gate Dead- time GL: H  L, GH(6): L  H 15 ns tPDHL High-Side to Low-side Gate Dead- time VSWH: H  1V, GL: L  H 13 ns tTSSHD Tri-State Shutdown Delay PWM: L  VTRI, GL: H  L and PWM: H  VTRI, VSWH: H  L 25 ns tTSEXIT Tri-State Propagation Delay PWM: VTRI  H, VSWH: L  H PWM: VTRI  L, GL: L  H 35 ns tLGMIN Low-Side Minimum On-Time SMOD# = L 350 ns Rev. 1.0 September 2019
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